CY7B9234
CY7B9334
SMPTE HOTLink
®
Transmitter/Receiver
Features
■
■
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■
■
■
■
■
■
■
■
■
■
■
■
SMPTE-259M-CD compliant along with SMPTE-259M
encoder (CY7C9235) and decoder (CY7C9335)
Fibre Channel compliant
DVB-ASI compliant
RX PLL tolerant of long run length data patterns (>20 bits)
8B/10B-coded or 10-bit unencoded
TTL synchronous I/O
No external PLL components
Triple PECL 100K serial outputs
Dual PECL 100K serial inputs
Low power: 350 mW (Tx), 650 mW (Rx)
Compatible with fiber-optic modules, coaxial cable, and twisted
pair media
Built-In Self-Test
Single +5V supply
28-pin PLCC
0.8μ BiCMOS
transfer uncompressed SMPTE-259M encoded video over
high-speed serial links (fiber, coax, and twisted pair). SMPTE
HOTLink supports SMPTE-259M-CD standard data rates at 270
and 360 Mbps.
Figure 1
illustrates typical connections to host
systems or controllers.
Eight or ten bits of user data or protocol information are loaded
into the SMPTE HOTLink transmitter and, in DVB mode, are
encoded. Serial data is shifted out of the three differential
positive ECL (PECL) serial ports at the bit rate (which is 10 times
the byte rate).
The SMPTE HOTLink receiver accepts the serial bit stream at its
differential line receiver inputs and, using a completely integrated
PLL Clock Synchronizer, recovers the timing information
necessary for data reconstruction. The bit stream is deserialized,
and in DVB mode, decoded and checked for transmission errors.
Recovered bytes are presented in parallel to the receiving host
along with a byte rate clock.
The 8B/10B encoder/decoder can be disabled in SMPTE or DVB
systems that already encode or scramble the transmitted data.
I/O signals are available to create a seamless interface with both
asynchronous FIFOs (i.e., CY7C42X) and clocked FIFOs (i.e.,
CY7C44X). A Built-In Self-Test pattern generator and checker
allows testing of the transmitter, receiver, and the connecting link
as a part of a system diagnostic check.
SMPTE HOTLink devices are ideal for a variety of video applica-
tions including video transmission equipment, video recorders,
video editing equipment, and video routers.
Functional Description
The CY7B9234 SMPTE HOTLink
®
Transmitter and CY7B9334
SMPTE HOTLink Receiver bolt on to the SMPTE Scrambler
Controller (CY7C9235) and SMPTE Descrambler/Framer
Controller (CY7C9335) completing the four piece chipset to
CY7B9234 Transmitter Logic Block Diagram
D
0− 7
(D
b
−
h
)
RP ENN
ENA
SC/D (D
a
)
SVS(D
j
)
FOTO
CY7B9334 Receiver Logic Block Diagram
RF
A/B
INA+
INA−
INB (INB+)
SI(INB− )
PECL
TTL
DATA
FRAMER
CKW
ENABLE
INPUT REGISTER
SHIFTER
DECODER
REGISTER
ENCODER
CLOCK
GENERATOR
SHIFTER
SO
OUTA
OUTB
OUTC
MODE
BISTEN
TEST
LOGIC
REFCLK
MODE
BISTEN
CLOCK
SYNC
DECODER
TEST
LOGIC
OUTPUT
REGISTER
CKR
RDY
Q
0− 7
(Q
b
−
h
)
RVS(Q
j
)
SC/D (Q
a
)
Cypress Semiconductor Corporation
Document #: 38-02014 Rev. *C
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised March 19, 2010
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CY7B9234
CY7B9334
Contents
Features ........................................................................... 1
Functional Description ................................................... 1
Contents .......................................................................... 2
CY7B9234 Transmitter Pin Configuration .................... 3
CY7B9334 Receiver Pin Configuration ......................... 3
Pin Description ............................................................... 3
CY7B9234 SMPTE HOTLink Transmitter ................. 3
Pin Description ............................................................... 5
CY7B9334 SMPTE HOTLink Receiver ..................... 5
CY7B9234 SMPTE HOTLink Transmitter
Block Diagram Description ............................................ 6
Input Register ............................................................ 6
Encoder ..................................................................... 6
Shifter ........................................................................ 6
OutA, OutB, OutC ...................................................... 6
Clock Generator ........................................................ 6
Test Logic .................................................................. 7
CY7B9334 SMPTE HOTLink Receiver
Block Diagram Description............................................ 7
Serial Data Inputs ...................................................... 7
PECL-TTL Translator ................................................ 7
Clock Synchronization ............................................... 7
Framer ....................................................................... 7
Shifter ........................................................................ 7
Decode Register ........................................................ 7
Decoder ..................................................................... 7
Output Register ......................................................... 8
Test Logic .................................................................. 8
Maximum Ratings ........................................................... 9
Operating Range ............................................................. 9
CY7B9234/CY7B9334 Electrical Characteristics ......... 9
Capacitance[7] .............................................................. 10
AC Test Loads and Waveforms ................................... 10
Transmitter Switching Characteristics ....................... 10
Receiver Switching Characteristics ............................ 11
Switching Waveforms for the CY7B9234
SMPTE HOTLink Transmitter ...................................... 12
Switching Waveforms for the CY7B9334
SMPTE HOTLink Receiver ........................................... 13
SMPTE HOTLink CY7B9234 Transmitter
and CY7B9334 Receiver Operation ............................. 14
CY7B9234 SMPTE HOTLink Transmitter
Operating Mode Description ....................................... 16
Encoded Mode Operation ....................................... 16
Bypass Mode Operation .......................................... 16
PECL Output Functional and Connection Options .. 17
Transmitter Serial Data Characteristics ..................... 18
Transmitter Test Mode Description ............................ 18
BIST Mode .............................................................. 19
Test Mode ............................................................... 20
CY7B9334 SMPTE HOTLink Receiver
Operating Mode Description ....................................... 20
Encoded Mode Operation ....................................... 20
Bypass Mode Operation .......................................... 20
Parallel Output Function .......................................... 21
Receiver Serial Data Requirements ............................ 21
Receiver Test Mode Description ................................. 21
BIST Mode .............................................................. 22
Test Mode ............................................................... 22
8B/10B Codes and Notation Conventions .................. 22
Notation Conventions .............................................. 22
8B/10B Transmission Code ..................................... 23
Transmission Order ................................................. 23
Valid and Invalid Transmission Characters ............. 23
Use of the Tables for Generating
Transmission Characters ........................................ 24
Use of the Tables for Checking the Validity
of Received Transmission Characters .................... 24
Valid Data Characters (SC/D = LOW) .......................... 24
Valid Special Character Codes and Sequences
(SC/D = HIGH)[24, 25] ................................................... 33
Ordering Information .................................................... 34
Package Diagram .......................................................... 34
Document History Page ............................................... 35
Sales, Solutions, and Legal Information .................... 35
Worldwide Sales and Design Support ..................... 35
Products .................................................................. 35
PSoC Solutions
....................................................... 35
Document #: 38-02014 Rev. *C
Page 2 of 35
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CY7B9234
CY7B9334
Figure 1. SMPTE HOTLink System Connections
PROTOCOL
LOGIC
SMPTE Serializer
CY7B9234
PROTOCOL
LOGIC
HOST
SMPTE Deserializer
CY7B9334
SMPTE Decoder
CY7C9335
SMPTE Encoder
CY7C9235
7B9234
TRANSMIT
MESSAGE
BUFFER
SERIAL LINK
HOST
CY7B9234 Transmitter Pin Configuration
PLCC
Top View
V
CCN
OUTC+
OUTC−
OUTB−
OUTB+
OUTA+
OUTA−
CY7B9334 Receiver Pin Configuration
PLCC
Top View
BISTEN
A/B
INA+
INA−
INB (INB+)
SI (INB−)
MODE
4 3 2 1 28 2726
BISTEN
GND
MODE
RP
V
CCQ
SVS(D
j
)
(D
h
)D
7
5
6
7
7B9234
8
9
10
11 1213 14 15 16 1718
25
24
23
22
21
20
19
FOTO
ENN
ENA
V
CCQ
CKW
GND
SC/D(D
a
)
4 3 2 1 28 2726
RF
GND
RDY
GND
V
CCN
RVS (Q
j
)
(Q
h
) Q
7
5
6
7
7B9334
8
9
10
11 1213 14 15 16 1718
(D
g
) D
6
(D
f
) D
5
(D
i
) D
4
(D
e
) D
3
(D
d
) D
2
(D
c
) D
1
(D
b
) D
0
Pin Description
CY7B9234 SMPTE HOTLink Transmitter
Name
D
0−7
(D
b
−
h
)
SC/D (D
a
)
I/O
TTL In
Description
Parallel Data Input.
Data is clocked into the Transmitter on the rising edge of CKW if ENA is LOW
(or on the next rising CKW with ENN LOW). If ENA and ENN are HIGH, a Null character (K28.5) is
sent. When MODE is HIGH, D
0, 1, ...7
become D
b, c,...h
respectively.
Special Character/Data Select.
A HIGH on SC/D when CKW rises causes the transmitter to encode
the pattern on D
0−7
as a control code (Special Character), while a LOW causes the data to be coded
using the 8B/10B data alphabet. When MODE is HIGH, SC/D (D
a
) acts as D
a
input. SC/D has the
same timing as D
0−7
.
Send Violation Symbol.
If SVS is HIGH when CKW rises, a Violation symbol is encoded and sent
while the data on the parallel inputs is ignored. If SVS is LOW, the state of D
0−7
and SC/D determines
the code sent. In normal or test mode, this pin overrides the BIST generator and forces the trans-
mission of a Violation code. When MODE is HIGH (placing the transmitter in unencoded mode), SVS
(D
j
) acts as the D
j
input. SVS has the same timing as D
0−7
.
Enable Parallel Data.
If ENA is LOW on the rising edge of CKW, the data is loaded, encoded, and
sent. If ENA and ENN are HIGH, the data inputs are ignored and the Transmitter will insert a Null
character (K28.5) to fill the space between user data. ENA may be held HIGH/LOW continuously or
it may be pulsed with each data byte to be sent. If ENA is being used for data control, ENN will normally
be strapped HIGH, but can be used for BIST function control.
TTL In
SVS
(D
j
)
TTL In
ENA
TTL In
Document #: 38-02014 Rev. *C
(Q
g
) Q
6
(Q
f
) Q
5
(Q
i
) Q
4
(Q
e
) Q
3
(Q
d
) Q
2
(Q
c
) Q
1
(Q
b
) Q
0
RECEIVE
MESSAGE
BUFFER
25
24
23
22
21
20
19
REFCLK
V
CCQ
SO
CKR
V
CCQ
GND
SC/D (Q
a
)
Page 3 of 35
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CY7B9234
CY7B9334
Pin Description
CY7B9234 SMPTE HOTLink Transmitter
(continued)
Name
ENN
I/O
TTL In
Description
Enable Next Parallel Data.
If ENN is LOW, the data appearing on D
0−7
at the next rising edge of
CKW is loaded, encoded, and sent. If ENA and ENN are HIGH, the data appearing on D
0−7
at the
next rising edge of CKW will be ignored and the Transmitter will insert a Null character to fill the space
between user data. ENN may be held HIGH/LOW continuously or it may be pulsed with each data
byte sent. If ENN is being used for data control, ENA will normally be strapped HIGH, but can be used
for BIST function control.
Clock Write.
CKW is both the clock frequency reference for the multiplying PLL that generates the
high-speed transmit clock, and the byte rate write signal that synchronizes the parallel data input.
CKW must be connected to a crystal controlled time base that runs within the specified frequency
range of the Transmitter and Receiver.
Fiber-Optic Transmitter Off.
FOTO determines the function of two of the three PECL transmitter
output pairs. If FOTO is LOW, the data encoded by the Transmitter will appear at the outputs contin-
uously. If FOTO is HIGH, OUTA± and OUTB± are forced to their “logic zero” state (OUT+ = LOW and
OUT− = HIGH), causing a fiber-optic transmit module to extinguish its light output. OUTC is unaffected
by the level on FOTO, and can be used as a loop-back signal source for board-level diagnostic testing.
Differential Serial Data Outputs.
These PECL 100K outputs (+5V referenced) are capable of driving
terminated transmission lines or commercial fiber-optic transmitter modules. Unused pairs of outputs
can be wired to V
CC
to reduce power if the output is not required. OUTA± and OUTB± are controlled by the
level on FOTO, and will remain at their “logical zero” states when FOTO is asserted. OUTC± is unaffected by
the level on FOTO (OUTA+ and OUTB+ are used as a differential test clock input while in Test mode, i.e.,
MODE=UNCONNECTED or forced to V
CC
/2).
Encoder Mode Select.
The level on MODE determines the encoding method to be used. When wired
to GND, MODE selects 8B/10B encoding. When wired to V
CC
, data inputs bypass the encoder and the
bit pattern on D
a–j
goes directly to the shifter. When left floating (internal resistors hold the input at V
CC
/2) the
internal bit-clock generator is disabled and OUTA+/OUTB+ become the differential bit clock to be used for
factory test. In typical applications MODE is wired to V
CC
or GND.
Built-In Self-Test Enable.
When BISTEN is LOW and ENA and ENN are HIGH, the transmitter sends an
alternating 1−0 pattern (D10.2 or D21.5). When either ENA or ENN is set LOW and BISTEN is LOW, the
transmitter begins a repeating test sequence that allows the Transmitter and Receiver to work together to test
the function of the entire link. In normal use this input is held HIGH or wired to V
CC
. The BIST generator is a
free-running pattern generator that need not be initialized, but if required, the BIST sequence can be initialized
by momentarily asserting SVS while BISTEN is LOW. BISTEN has the same timing as D
0−7
.
Read Pulse.
RP is a 60% LOW duty-cycle byte-rate pulse train suitable for the read pulse in CY7C42X
FIFOs. The frequency on RP is the same as CKW when enabled by ENA, and duty cycle is independent of
the CKW duty cycle. Pulse widths are set by logic internal to the transmitter. In BIST mode, RP will remain
HIGH for all but the last byte of a test loop. RP will pulse LOW one byte time per BIST loop.
Power for output drivers.
Power for internal circuitry.
Ground.
CKW
TTL In
FOTO
TTL In
OUT A±
OUT B±
OUT C±
PECL Out
MODE
3-Level In
BISTEN
TTL In
RP
TTL Out
V
CCN
V
CCQ
GND
Document #: 38-02014 Rev. *C
Page 4 of 35
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CY7B9234
CY7B9334
Pin Description
CY7B9334 SMPTE HOTLink Receiver
Name
Q
0−7
(Q
b
−
h
)
SC/D(Q
a
)
I/O
TTL Out
TTL Out
Description
Q
0−7
Parallel Data Output.
Q
0−7
contain the most recently received data. These outputs change synchro-
nously with CKR. When MODE is HIGH, Q
0, 1, ...7
become Q
b, c,...h
respectively.
Special Character/Data Select.
SC/D indicates the context of received data. HIGH indicates a Control
(Special Character) code, LOW indicates a Data character. When MODE is HIGH (placing the receiver in
Unencoded mode), SC/D acts as the Q
a
output. SC/D has the same timing as Q
0−7
.
Received Violation Symbol.
A HIGH on RVS indicates that a code rule violation has been detected
in the received data stream. A LOW shows that no error has been detected. In BIST mode, a LOW
on RVS indicates correct operation of the Transmitter, Receiver, and link on a byte-by-byte basis.
When MODE is HIGH (placing the receiver in Unencoded mode), RVS acts as the Q
j
output. RVS has
the same timing as Q
0−7
.
Data Output Ready.
A LOW pulse on RDY indicates that new data has been received and is ready to be
delivered. A missing pulse on RDY shows that the received data is the Null character (normally inserted by
the transmitter as a pad between data inputs). In BIST mode RDY will remain LOW for all but the last byte of
a test loop and will pulse HIGH one byte time per BIST loop.
Clock Read.
This byte rate clock output is phase and frequency aligned to the incoming serial data
stream. RDY, Q
0−7
, SC/D, and RVS all switch synchronously with the rising edge of this output.
Serial Data Input Select.
This PECL 100K (+5V referenced) input selects INA or INB as the active
data input. If A/B is HIGH, INA is connected to the shifter and signals connected to INA will be decoded. If
A/B is LOW INB is selected.
Serial Data Input A.
The differential signal at the receiver end of the communication link may be
connected to the differential input pairs INA± or INB±. Either the INA pair or the INB pair can be used as
the main data input and the other can be used as a loopback channel or as an alternative data input selected
by the state of A/B.
Serial Data Input B.
This pin is either a single-ended PECL data receiver (INB) or half of the INB
differential pair. If SO is wired to V
CC
, then INB± can be used as differential line receiver interchangeably
with INA±. If SO is normally connected and loaded, INB becomes a single-ended PECL 100K (+5V refer-
enced) serial data input. INB is used as the test clock while in Test mode.
Status Input.
This pin is either a single-ended PECL status monitor input (SI) or half of the INB
differential pair. If SO is wired to V
CC
, then INB± can be used as differential line receiver inter-
changeably with INA±. If SO is normally connected and loaded, SI becomes a single-ended PECL
100K (+5V referenced) status monitor input, which is translated into a TTL-level signal at the SO pin.
Status Out.
SO is the TTL-translated output of SI. It is typically used to translate the Carrier Detect
output from a fiber-optic receiver connected to SI. When this pin is normally connected and loaded
(without any external pull-up resistor), SO will assume the same logical level as SI and INB will become
a single-ended PECL serial data input. If the status monitor translation is not desired, then SO may
be wired to V
CC
and the INB± pair may be used as a differential serial data input.
Reframe Enable.
RF controls the Framer logic in the Receiver. When RF is held HIGH, each SYNC
(K28.5) symbol detected in the shifter will frame the data that follows. If is HIGH for 2,048 consecutive
bytes, the internal framer switches to double-byte mode. When RF is held LOW, the reframing logic
is disabled. The incoming data stream is then continuously deserialized and decoded using byte
boundaries set by the internal byte counter. Bit errors in the data stream will not cause alias SYNC
characters to reframe the data erroneously.
Reference Clock.
REFCLK is the clock frequency reference for the clock/data synchronizing PLL.
REFCLK sets the approximate center frequency for the internal PLL to track the incoming bit stream.
REFCLK must be connected to a crystal-controlled time base that runs within the frequency limits of
the Tx/Rx pair, and the frequency must be the same as the transmitter CKW frequency (within
CKW±0.1%)
Decoder Mode Select.
The level on the MODE pin determines the decoding method to be used.
When wired to GND, MODE selects 8B/10B decoding. When wired to V
CC
, registered shifter contents
bypass the decoder and are sent to Q
a−j
directly. When left floating (internal resistors hold the MODE pin at
V
CC
/2) the internal bit clock generator is disabled and INB becomes the bit rate test clock to be used for factory
test. In typical applications, MODE is wired to V
CC
or GND.
RVS (Q
j
)
TTL Out
RDY
TTL Out
CKR
A/B
TTL Out
PECL in
INA±
Diff In
INB
(INB+)
PECL in
(Diff In)
SI
(INB−)
PECL in
(Diff In)
SO
TTL Out
RF
TTL In
REFCLK
TTL In
MODE
3-Level In
Document #: 38-02014 Rev. *C
Page 5 of 35
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