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PRELIMINARY
CY2DP818-2
1:8 Clock Fanout Buffer
Features
■
■
■
■
■
■
■
■
■
■
■
■
Description
This Cypress series of network circuits is produced using
advanced 0.35 micron CMOS technology, achieving the
industry’s fastest logic.
The Cypress CY2DP818-2 fanout buffer features a single
LVDS or a single-ended LVTTL compatible input and eight
LVPECL output pairs.
Designed for data communications clock management appli-
cations, the large fanout from a single input reduces loading
on the input clock.
The CY2DP818-2 is ideal for both level translations from
single-ended to LVPECL and for the distribution of LVPECL
based clock signals.
The Cypress CY2DP818-2 has configurable input functions.
The input is user configurable through the Inconfig pin for
single ended or differential input.
Low voltage operation V
DD
= 3.3V
1:8 fanout
Single-input configurable for LVDS, LVPECL, or LVTTL
8 pairs of LVPECL outputs with enable and disable
Drives a 50 ohm load
Low input capacitance
Low output skew
Low propagation delay typical (tpd < 4 ns)
Industrial versions available
Package available include: TSSOP
Does not exceed Bellcore 802.3 standards
Operation up to 350 MHz and 700 Mbps
Logic Block Diagram
EN1
Q1A
Q1B
EN2
Q2A
Q2B
EN3
INPUT
(LVPECL / LVDS / LVTTL)
Q3A
Q3B
Q4A
Q4B
EN4
INPUT A
INPUT B
EN5
Q5A
Q5B
InConfig
EN6
Q6A
Q6B
EN7
Q7A
Q7B
Q8A
Q8B
OUTPUT
(LVPECL)
Cypress Semiconductor Corporation
Document #: 38-07588 Rev. *A
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised October 22, 2008
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PRELIMINARY
CY2DP818-2
Pin Configuration
Figure 1. Pin Diagram - 38-Pin TSSOP
GND
VDD
EN1
EN2
EN3
EN4
InConfig
VDD
GND
INPUT A
INPUT B
GND
VDD
EN5
EN6
EN7
VDD
GND
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
GND
Q1A
Q1B
Q2A
Q2B
Q3A
Q3B
Q4A
Q4B
VDD
Q5A
Q5B
Q6A
Q6B
Q7A
Q7B
Q8A
Q8B
GND
CY2DP818-2
Pin Description
Pin Number
2,8,13,29,17
3,4,5,6,14,15,16
VDD
EN(1:7)
Pin Name
Pin Standard Interface
POWER
POWER
LVTTL/LVCMOS
Ground.
Power supply.
The respective outputs are enabled when these
pins are pulled high.
Outputs are disabled when
connected to GND. EN7 controls both Q7(A,B) and
Q8(A,B)
Differential input pair or single line.
LVPECL/LVDS
default. See InConfig, below.
Differential outputs.
Description
1, 9,12,18,19,20,38 GND
10,11
Input A, Input B
Default: LVPECL/LDVS
Optional: LVTTL/LVCMOS
single pin
LVPECL
37, 36,35,34,
33,32,31, 30,
28,27,26,25,
24,23,22,21
7
Q1(A,B), Q2(A,B)
Q3(A,B), Q4(A,B)
Q5(A,B), Q6(A,B)
Q7(A,B), Q8(A,B)
InConfig
LVTTL/LVCMOS
Converts inputs from the default
LVPECL/LVDS (logic = 0)
to LVTTL/LVCMOS (logic = 1)
See
Input Receiver Configuration for Differential or
LVTTL/LVCMOS
table,
Figure 6
and
Figure 7
for
additional information
Document #: 38-07588 Rev. *A
Page 2 of 9
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PRELIMINARY
CY2DP818-2
Power Supply Characteristics
Parameter
ICCD
IC
Description
Dynamic Power Supply Current
Total Power Supply Current
Test Conditions
V
DD
= Max.
Input toggling 50% Duty Cycle, Outputs Open
V
DD
= Max.
Input toggling 50% Duty Cycle, Outputs 50 ohms,
fL=100 MHz
V
DD
= Max.
Input toggling 50% Duty Cycle, Outputs Disabled,
not connected to VTT fL = 100 MHz
Min
Typ
1.5
Max
2.0
350
Unit
mA/
MHz
mA
IC Core
Core Current when Output Loads
are Disabled
50
mA
Input Receiver Configuration for Differential or LVTTL/LVCMOS
INCONFIG Pin 7
Binary Value
1
0
Input Receiver Family
LVTTL in LVCMOS
LVDS
LVPECL
Input Receiver Type
Single ended, non inverting, inverting, void of bias resistors
Low voltage differential signaling
Low voltage pseudo (positive) emitter coupled logic
Function Control of the TTL Input Logic used to Accept or Invert the Input Signal
LVTTL/LVCMOS Input Logic
Input Condition
Ground
V
DD
Ground
V
DD
Input B (–) Pin 11
Input A (+) Pin 10
Input B (–) Pin 11
Input A (+) Pin 10
Input A (+) Pin 10
Input B (–) Pin 11
Input A (+) Pin 10
Input B (–) Pin 11
Input
True
Input
Invert
Input
Invert
Input
True
Input Logic
Output Logic Q Pins, Q1A or Q1
Document #: 38-07588 Rev. *A
Page 3 of 9
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PRELIMINARY
CY2DP818-2
Absolute Maximum Conditions
Parameter
V
DD
V
DD
V
IN
V
OUT
V
TT
T
S
T
A
Description
DC Supply Voltage
DC Operating Voltage
DC Input Voltage
DC Output Voltage
Output Termination Voltage
Temperature, Storage
Temperature, Operating
Ambient
Industrial
Non Functional
Commercial Functional
Functional
Outputs
Relative to V
SS
, with or V
DD
applied
Relative to V
SS
Condition
Inputs and V
CC
Min
–0.3
–0.3
–0.3
–0.3
–
–65
0
–40
Max
4.6
V
DD
+ 0.3
V
DD
+ 0.3
V
DD
+ 0.9
V
DD
÷
2
+150
70
+85
Unit
V
V
V
V
V
°C
°C
Multiple Supplies:
The voltage on any input or I/O pin cannot exceed the power pin during power up. Power supply sequencing is
NOT required.
DC Electrical Specifications
3.3V – LVDS Input at V
DD
= 3.3V ± 5%, T
A
= 0°C to 70°C or –40°C to 85°C
Parameter
V
ID
V
IC
I
IH
I
IL
Description
Magnitude of Differential Input Voltage
Common Mode of Differential Input
VoltageIV
ID
I
(minimum and maximum)
Input High Current
Input Low Current
V
DD
= Max.
V
DD
= Max.
V
IN
= V
DD
V
IN
= V
SS
Conditions
Min
100
IVIDI/2
–
–
Typ
Max
600
2.4–(IVIDI/2)
±10
±10
± 20
± 20
Unit
mV
V
μA
μA
3.3V – LVPECL Input at V
DD
= 3.3V ± 5%, T
A
= 0°C to 70°C or –40°C to 85°C
Parameter
V
ID
V
IH
V
IL
I
IH
I
IL
V
CM
Description
Differential Input Voltage p-p
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Common-mode Voltage
Conditions
Guaranteed Logic High Level
Guaranteed Logic High Level
Guaranteed Logic Low Level
V
DD
= Max.
V
DD
= Max.
V
IN
= V
DD
V
IN
= V
SS
Min
400
2.15
1.5
–
–
1650
Typ
–
–
–
±10
±10
–
Max
2600
2.4
1.8
±20
±20
2250
Unit
mV
V
V
μA
μA
mV
3.3V – LVTTL/LVCMOS Input at V
DD
= 3.3V ± 5%, T
A
= 0°C to 70°C or –40°C to 85°C
Parameter
V
IH
V
IL
I
IH
I
IL
I
I
V
IK
V
H
Description
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input High Current
Clamp Diode Voltage
Input
Hysteresis
[1]
Conditions
Guaranteed Logic High Level
Guaranteed Logic Low Level
V
DD
= Max
V
DD
= Max
V
DD
= Max, V
IN
= V
DD
(Max)
V
DD
= Min, I
IN
= –18 mA
–
–
–0.7
80
–1.2
V
mV
V
IN
= 2.7V
V
IN
= 0.5V
Min
2
–
–
–
Typ
–
–
–
–
Max
–
0.8
1
–1
Units
V
V
μA
μA
Note
1. Guaranteed but not tested.
Document #: 38-07588 Rev. *A
Page 4 of 9
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