78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
PRELIMINARY DATASHEET
FEBRUARY 2004
DESCRIPTION
The 78P2352 is TDK’s second generation Line
Interface Unit (LIU) for 155 Mbit/s SDH/SONET (OC-
3, STS-3, or STM-1) and 140 Mbit/s PDH (E4)
applications. The device is a dual channel, single
chip solution that includes an integrated CDR in the
transmit path for flexible NRZ to CMI conversion.
The device can interface to 75Ω coaxial cable using
CMI coding or directly to a fiber optics module using
NRZ coding. The 78P2352 is compliant with all
respective ANSI, ITU-T, and Telcordia standards for
jitter tolerance, generation, and transfer.
APPLICATIONS
•
•
•
•
Central Office Interconnects
DSLAMs
Add Drop Multiplexers (ADMs)
Multi Service Switches
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
BLOCK DIAGRAM
Lock Detect
SIxDP/N
SIxCKP/N
PIxCK
PIx[3:0]D
PTOxCK
Tx CDR
EACH CHANNEL: Tx
ECLxP/N
G.703 compliant, adjustable cable driver for
139.264 Mbps or 155.52 Mbps CMI-coded coax
transmission
Integrated adaptive CMI equalizer and CDR in
receive path handles over 15dB of cable loss
Serial, LVPECL system interface with integrated
CDR in transmit path for flexible NRZ to CMI
conversion.
4-bit parallel CMOS system interface with
master/slave Tx clock modes.
Selectable LVPECL compatible NRZ line
interface for 155.52 Mbps optical transmission.
Configurable via HW control pins or 4-wire serial
port interface
Optional fixed backplane equalizer compensates
for up to 1.5m of trace
Compliant with ANSI T1.105.03-1994; ITU-T
G.751, G.813, G.823, G.825, G.958; and
Telcordia GR-253-CORE for jitter performance.
Loss of Lock (LOL) and standards compliant
Loss of Signal (LOS) detection.
Receive Monitor Mode handles up to 20dB of
flat loss (at max 6dB cable loss)
Operates from a single 3.3V supply
Standard and thermally enhanced 128-pin
JEDEC LQFP
FIFO
CMI
Encoder
TXxCKP/N
CMIxP/N
PMOD, SMOD[1:0], PAR
RLBK
SOxCKP/N
SOxDP/N
POx[3:0]D
POxCK
CMI
Decoder
Rx CDR
Lock Detect
CMI
EACH CHANNEL: Rx
Adaptive
Eq.
RXxP/N
LOS Detect
LLBK
1
78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit
TABLE OF CONTENTS ................................................................................................ 2
FUNCTIONAL DESCRIPTION........................................................................................ 4
MODE SELECTION................................................................................................................................4
REFERENCE CLOCK ............................................................................................................................4
RECEIVER OPERATION .......................................................................................................................4
Receiver Monitor Mode ..................................................................................................................4
Loss of Signal .................................................................................................................................4
Loss of Lock....................................................................................................................................4
TRANSMITTER OPERATION ................................................................................................................5
Synchronous Serial Modes ...........................................................................................................5
Plesiochronous Serial Modes .......................................................................................................5
Parallel Modes.................................................................................................................................6
Transmit Driver ...............................................................................................................................6
Pulse Amplitude Adjustment.........................................................................................................6
Clock Synthesizer...........................................................................................................................6
Transmit Backplane Equalizer ......................................................................................................6
Transmit Loss of Lock ...................................................................................................................6
POWER-DOWN FUNCTION .................................................................................................................6
LOOPBACK MODES .............................................................................................................................7
POWER-ON RESET ..............................................................................................................................7
SERIAL CONTROL INTERFACE .........................................................................................................7
PROGRAMMABLE INTERRUPTS ........................................................................................................7
REGISTER DESCRIPTION............................................................................................. 8
REGISTER ADDRESSING.....................................................................................................................8
REGISTER TABLE.................................................................................................................................8
LEGEND .................................................................................................................................................9
GLOBAL REGISTERS ...........................................................................................................................9
ADDRESS 0-0: MASTER CONTROL REGISTER .........................................................................9
ADDRESS 0-1: INTERRUPT CONTROL REGISTER..................................................................10
PORT-SPECIFIC REGISTERS.............................................................................................................11
ADDRESS N-0: MODE CONTROL REGISTER...........................................................................11
ADDRESS N-1: SIGNAL CONTROL REGISTER ........................................................................12
ADDRESS N-2: ADVANCED TX CONTROL REGISTER 1 ........................................................13
ADDRESS N-3: ADVANCED TX CONTROL REGISTER 0 ........................................................13
ADDRESS N-4: MODE CONTROL REGISTER 2........................................................................13
ADDRESS N-5: STATUS MONITOR REGISTER ........................................................................14
PIN DESCRIPTION ....................................................................................................... 15
LEGEND ...............................................................................................................................................15
TRANSMITTER PINS ...........................................................................................................................15
RECEIVER PINS ..................................................................................................................................16
REFERENCE AND STATUS PINS ......................................................................................................17
CONTROL PINS ..................................................................................................................................18
SERIAL-PORT PINS ............................................................................................................................20
POWER AND GROUND PINS .............................................................................................................20
2
78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit
TABLE OF CONTENTS
(continued)
ELECTRICAL SPECIFICATIONS ................................................................................. 21
ABSOLUTE MAXIMUM RATINGS..........................................................................................................21
RECOMMENDED OPERATING CONDITIONS ......................................................................................21
DC CHARACTERISTICS.........................................................................................................................21
ANALOG PINS CHARACTERISTICS .....................................................................................................22
DIGITAL I/O CHARACTERISTICS..........................................................................................................22
Pins of type CI, CIU, CID................................................................................................................22
Pins of type CIT ..............................................................................................................................22
Pins of type CIS ..............................................................................................................................22
Pins of type CO and COZ...............................................................................................................23
Pins of type PO...............................................................................................................................23
Pins of type PI.................................................................................................................................23
Pins of type OD...............................................................................................................................23
SERIAL-PORT TIMING CHARACTERISTICS........................................................................................24
TRANSMITTER TIMING CHARACTERISTICS ......................................................................................25
TIMING DIAGRAM: Transmitter Waveforms .......................................................................................25
REFERENCE CLOCK CHARACTERISTICS..........................................................................................26
RECEIVER TIMING CHARACTERISTICS..............................................................................................26
TIMING DIAGRAM: Receive Waveforms ............................................................................................26
TRANSMITTER SPECIFICATIONS FOR CMI INTERFACE .................................................................27
TRANSMITTER OUTPUT JITTER ..........................................................................................................32
RECEIVER SPECIFICATIONS FOR CMI INTERFACE (Transformer-coupled) ..................................33
RECEIVER JITTER TOLERANCE ..........................................................................................................34
RECEIVER JITTER TRANSFER FUNCTION .........................................................................................36
CMI MODE LOSS OF SIGNAL CONDITION ..........................................................................................37
APPLICATION INFORMATION .................................................................................... 37
EXTERNAL COMPONENTS ...................................................................................................................37
TRANSFORMER SPECIFICATIONS ......................................................................................................37
THERMAL INFORMATION .....................................................................................................................37
MECHANICAL SPECIFICATIONS ............................................................................... 38
PACKAGE INFORMATION
(pinout)................................................................................................
40
ORDERING INFORMATION ......................................................................................... 40
Revision History
........................................................................................................................................41
3
78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit
FUNCTIONAL DESCRIPTION
The 78P2352 contains all the necessary transmit
and receive circuitry for connection between
139.264Mbit/s and 155.52Mbit/s line interfaces and
the digital universe. The chip is controllable through
pins or serial port register settings.
In hardware mode (pin control) the SPSL pin
must be low.
In software mode (SPSL pin high), control pins
are disabled and the 78P2352 must be
configured via the 4-wire serial port.
MODE SELECTION
The SDO_E4 pin or E4 register bit determines which
rate the device operates in according to the table
below. This control combined with CKSL also
selects the global reference frequency.
Rate
E4
STM-1, STS-3, OC-3
SDO_E4 pin
High
Low
E4 bit
1
0
RECEIVER OPERATION
The receiver accepts serial data, at 155.52Mbit/s or
139.264Mbit/s from the RXxP/N inputs. In CMI
mode, the CMI-coded inputs come from a coaxial
cable that is transformer-coupled to the chip. In NRZ
(optical) mode, the input pins receive NRZ LVPECL
level signals from an O/E converter.
The CMI signal first enters an AGC and a high
performance adaptive equalizer designed to
overcome inter-symbol interference caused by long
cable lengths. The variable gain differential amplifier
automatically controls the gain to maintain a
constant voltage level output regardless of the input
voltage level. In ECL (NRZ) mode, the input signals
bypass the adaptive equalizer.
The outputs of the data comparators are connected
to the clock recovery circuits. The clock recovery
system employs a digital PLL, which uses a
reference frequency derived from the clock applied
to the CKREFP/N pins.
In serial mode, the clock and data are transmitted
through the LVPECL drivers. In parallel mode, the
data is converted into four bit parallel segments
before being transmitted through the CMOS drivers.
Receiver Monitor Mode
In CMI mode, the SCK_MON pin or MONx register
bit puts the receiver in monitor mode and adds
approximately 20dB of flat gain to the receive signal
before equalization. Rx Monitor Mode can handle
20dB of flat loss typical of monitoring points with up
to 6dB of cable loss. Note that Loss of Signal
detection is disabled during Rx Monitor Mode.
Loss of Signal
The 78P2352 includes a ITU-T G.775/G.783
compliant Loss of Signal (LOS) detector. When the
received CMI signal is less than approximately 18dB
below nominal for 80 UI, the LOS pin is asserted.
The LOS signal is cleared when the received signal
is greater than approximately 17dB below nominal
for 80 UI. During LOS conditions, the receive data
outputs are squelched and held at logic ‘0’.
Note:
Loss of Signal detection is disabled during
Local Loopback and Receive Monitor Modes.
In ECL mode, the LOSx signal will be asserted when
there are no transitions for longer than 2.3µs. The
signal is cleared when there are more than 4
transitions in 32 UI.
Loss of Lock
The 78P2352 will declare a loss of lock condition
when the recovered clock frequency differs from the
reference clock by more than
±100ppm
in an interval
greater than 420µs. This condition is cleared when
the frequencies are less than
±100ppm
off for more
than 500µs.
4
The SEN_CMI pin or CMI register bit selects one of
two media for reception and transmission: coaxial
cable in CMI mode or optical fiber in ECL (NRZ)
mode. Independent channel operation is available
with register controls.
Media (coding)
75 ohm Coax (CMI)
Fiber (NRZ)
SEN_CMI pin
High
Low
CMI bit
1
0
The SDI_PAR pin or PAR register bit selects the
interface to the framer to be four-bit parallel CMOS
or serial LVPECL. For each interface there are
different transmit timing modes See TRANSMITTER
OPERATION section for more info.
REFERENCE CLOCK
The 78P2352 requires a reference clock supplied to
the CKREFP/N pins. For reference frequencies of
77.76MHz or lower, the device accepts a single
ended CMOS input at CKREFP. For reference
frequencies of 139.264/155.52MHz, the device
accepts a differential LVPECL clock input at
CKREFP/N. The frequency of this reference input is
controlled by the rate selection and the CKSL control
pin or register bit.
CKSL pin
Low
Float
High
CKSL[1:0] bits
00
10
11
Reference Frequency
SDO_E4 low
SDO_E4 high
19.44MHz
77.76MHz
155.52MHz
E4 bit = 0
19.44MHz
77.76MHz
155.52MHz
17.408MHz
N/A
139.264MHz
E4 bit = 1
17.408MHz
N/A
139.264MHz
78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit
FUNCTIONAL DESCRIPTION
(continued)
TRANSMITTER OPERATION
The transmitter section generates an analog signal
for transmission through either a transformer onto
the coaxial cable using CMI coding or directly to a
fiber optics module using NRZ coding.
The 78P2352 provides a flexible system interface for
compatibility with most off-the-shelf framers and
custom ASICs. The device supports a 4-bit parallel
interface in either slave or master clocking modes
and a number of serial NRZ timing modes.
Each of the serial NRZ transmit timing modes can be
configured in HW mode or SW mode as shown in
the table below.
Serial
Mode
Synchronous
clock + data
Synchronous
data only
Plesiochronou
s data only
Loop-timing
If no serial transmit clock is available, as in
Figure 2,
the 78P2352 can recover a clock from the serial
NRZ data input and pass the data through the FIFO.
In this mode, the NRZ transmit data should be
source synchronous with the reference clock applied
at CKREFP/N. Each transmitter also includes a
Loss of Lock indicator (TXLOL) that can be used to
trigger an interrupt.
Note that the FIFO is
automatically re-centered when the TXLOL register
bit transitions from high to low.
System Reference Clock
CKREFP/N
NRZ
SIxDP/N
CMIxP/N
CMI
XFMR
Coax
Framer/
Mapper
NRZ
140 / 155 MHz
SOxCKP/N
SOxDP/N
TDK
78P2352
RXxP/N
CMI
XFMR
Coax
HW Control Pins SW Control Bits
SDI_PAR
Low
CKMODE
Low
PAR
0
SMOD[1:0]
00
Figure 2: Synchronous; data only
(Tx CDR enabled, FIFO enabled)
Low
Floating
0
10
Low
High
0
01
n/a
n/a
X
11
Synchronous Serial Modes
In Figure 1, serial NRZ transmit data is input to
SIDxP/N pins at LVPECL levels. By default, the data
is latched in on the rising edge of SICKxP. A clock
decoupling FIFO is provided to decouple the on chip
and off chip clocks. The SICKxP/N clock provided
by the framer/mapper IC must be source
synchronous with the internal reference transmit
clock if the FIFO is to be used.
System Reference Clock
Since the reference clock and transmit clock/data go
through different delay paths, it is inevitable that the
phase relationship between the two clocks can vary
in a bounded manner due to the fact that the
absolute delays in the two paths can vary over time.
The FIFO allows long-term clock phase drift, not
exceeding +/- 25.6ns, to be handled without transmit
error. If the clock wander exceeds the specified
limits, the FIFO will over or under flow, and the
FERRx register signal will be asserted. This signal
can be used to trigger an interrupt. This interrupt
event is cleared when an FRSTx pulse is applied,
and the FIFO is re-centered.
Note:
External remote loopbacks (i.e. loopback
within framer) are not possible in synchronous
operation (FIFO enabled) unless the reference
clock is synchronous with the recovered receive
clock (loop-timing).
Plesiochronous Serial Mode
Figure 3 represents the condition where no serial
transmit clock is available and the data is not source
synchronous to the reference clock input. In this
mode, the 78P2352 will recover a clock from the
serial plesiochronous data and bypass the FIFO.
Reference
Clock
XO
CKREFP
CKREFP/N
NRZ
SIxDP/N
CMI
CMIxP/N
140 / 155 MHz
XFMR
Coax
Framer/
Mapper
SIxCKP/N
NRZ
140 / 155 MHz
SOxCKP/N
SOxDP/N
TDK
78P2352
RXxP/N
CMI
XFMR
Coax
Figure 1: Synchronous; clock and data available
(Tx CDR bypassed, FIFO enabled)
NRZ
SIxDP/N
CMIxP/N
CMI
XFMR
Coax
Framer/
Mapper
NRZ
140 / 155 MHz
SOxCKP/N
SOxDP/N
TDK
78P2352
RXxP/N
CMI
XFMR
Coax
Figure 3: Plesiochronous; data only
(Tx CDR enabled, FIFO bypassed)
5
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
