78P2351R
155M NRZ to
CMI Converter
PRELIMINARY DATASHEET
FEBRUARY 2004
DESCRIPTION
The 78P2351R is TDK’s second generation Line
Interface Unit (LIU) for 155 Mbit/s electrical SDH
interfaces (STM1e). The device is a single chip
solution that includes an integrated Clock & Data
Recovery in the transmit path for easy, cost efficient
NRZ to CMI conversion.
The device interfaces to 75Ω coaxial cable through
wideband transformers and can handle over 15dB of
cable loss.
By integrating CDR capabilities in the transmit path,
the small 78P2351R (7x7mm MLF package) is also
ideal for new STM1e Small Form-factor Pluggable
(SFP) modules.
APPLICATIONS
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STM1e SFP modules
SDH/ATM Line Cards
Add Drop Multiplexers (ADMs)
PDH/SDH test equipment
FEATURES
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BLOCK DIAGRAM
G.703 compliant, adjustable cable driver for
155.52 Mbps CMI-coded coax transmission
Integrated adaptive CMI equalizer and CDR in
receive path handles over 15dB of cable loss
Serial, LVPECL-compatible system interface
with integrated CDR in transmit path for flexible
NRZ to CMI conversion
Configurable via HW control pins or 4-wire serial
port interface
Compliant with ANSI T1.105.03-1994; ITU-T
G.813, G.825, G.958; and Telcordia GR-253-
CORE for jitter performance
Provides G.783 compliant Loss of Signal (LOS)
detection
Receive Monitor Mode handles up to 20dB of
flat loss (at max 6dB cable loss)
Optional fixed backplane equalizer compensates
for up to 1.5m of trace
Operates from a single 3.3V supply
Available in a small 7x7mm 56-pin QFN
package
Industrial Temperature: -40˚C to +85˚C
75ohm Coax
(CMI Encoded)
78P2351R
Tx Disable
Fixed
Eq.
CDR
TD +
TD -
Adaptive
Eq.
CMI
ENDEC
CDR
RD +
RD -
Rx LOS
LVPECL Data
(NRZ Encoded)
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78P2351R 155Mbps NRZ to CMI Converter
TABLE OF CONTENTS ................................................................................................ 2
FUNCTIONAL DESCRIPTION........................................................................................ 4
REFERENCE CLOCK ............................................................................................................................4
RECEIVER OPERATION .......................................................................................................................4
Receiver Monitor Mode ..................................................................................................................4
Loss of Signal ................................................................................................................................4
TRANSMITTER OPERATION ................................................................................................................4
Plesiochronous Mode ....................................................................................................................5
Synchronous Mode ........................................................................................................................5
Clock Synthesizer...........................................................................................................................5
Pulse Amplitude Adjustment.........................................................................................................5
Transmit Backplane Equalizer ......................................................................................................5
POWER-DOWN FUNCTION .................................................................................................................5
LOOPBACK MODES .............................................................................................................................6
POWER-ON RESET ..............................................................................................................................6
SERIAL CONTROL INTERFACE .........................................................................................................6
REGISTER DESCRIPTION............................................................................................. 7
REGISTER ADDRESSING.....................................................................................................................7
REGISTER TABLE.................................................................................................................................7
LEGEND .................................................................................................................................................8
GLOBAL REGISTERS ...........................................................................................................................8
ADDRESS 0-0: MASTER CONTROL REGISTER .........................................................................8
PORT-SPECIFIC REGISTERS...............................................................................................................9
ADDRESS 1-0: MODE CONTROL REGISTER .............................................................................9
ADDRESS 1-1: SIGNAL CONTROL REGISTER.........................................................................10
ADDRESS 1-2: ADVANCED TX CONTROL REGISTER 1 .........................................................10
ADDRESS 1-3: ADVANCED TX CONTROL REGISTER 0 .........................................................11
ADDRESS 1-4: RESERVED.........................................................................................................11
ADDRESS 1-5: STATUS MONITOR REGISTER.........................................................................11
PIN DESCRIPTION ....................................................................................................... 12
LEGEND ...............................................................................................................................................12
TRANSMITTER PINS ...........................................................................................................................12
RECEIVER PINS ..................................................................................................................................12
REFERENCE AND STATUS PINS ......................................................................................................12
CONTROL PINS ..................................................................................................................................13
SERIAL-PORT PINS ............................................................................................................................14
POWER AND GROUND PINS .............................................................................................................14
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78P2351R 155Mbps NRZ to CMI Converter
TABLE OF CONTENTS
(continued)
ELECTRICAL SPECIFICATIONS ................................................................................. 15
ABSOLUTE MAXIMUM RATINGS..........................................................................................................15
RECOMMENDED OPERATING CONDITIONS ......................................................................................15
DC CHARACTERISTICS.........................................................................................................................15
ANALOG PINS CHARACTERISTICS .....................................................................................................16
DIGITAL I/O CHARACTERISTICS..........................................................................................................16
Pins of type CI, CID ........................................................................................................................16
Pins of type CIT ..............................................................................................................................16
Pins of type CIS ..............................................................................................................................16
Pins of type COZ ............................................................................................................................16
Pins of type PO...............................................................................................................................17
Pins of type PI.................................................................................................................................17
Pins of type OD...............................................................................................................................17
REFERENCE CLOCK CHARACTERISTICS..........................................................................................17
SERIAL-PORT TIMING CHARACTERISTICS........................................................................................18
TRANSMITTER SPECIFICATIONS FOR CMI INTERFACE .................................................................19
TRANSMITTER OUTPUT JITTER ..........................................................................................................22
RECEIVER SPECIFICATIONS FOR CMI INTERFACE (Transformer-coupled) ..................................23
RECEIVER JITTER TOLERANCE ..........................................................................................................24
RECEIVER JITTER TRANSFER FUNCTION .........................................................................................25
LOSS OF SIGNAL CONDITIONS ...........................................................................................................26
APPLICATION INFORMATION .................................................................................... 26
EXTERNAL COMPONENTS ...................................................................................................................26
TRANSFORMER SPECIFICATIONS ......................................................................................................26
THERMAL INFORMATION .....................................................................................................................26
MECHANICAL SPECIFICATIONS ............................................................................... 27
PACKAGE INFORMATION .......................................................................................... 28
ORDERING INFORMATION
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28
Revision History
........................................................................................................................................29
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78P2351R 155Mbps NRZ to CMI Converter
FUNCTIONAL DESCRIPTION
The 78P2351R contains all the necessary transmit
and receive circuitry for connection between
155.52Mbit/s NRZ data sources (STS-3/STM-1) and
CMI encoded electrical interfaces. The 78P2351R
system interface mimics a 3.3V optics module and
only requires a reference clock and wideband
transformer to complete the electrical interface. The
chip can be controlled via control pins or serial port
register settings.
In hardware mode (pin control) the SPSL pin must
be low. Additionally, the following unused pins
must be set accordingly:
SDO pin must be tied low
SDI pin must be tied low
SEN pin must be tied high
In software mode (SPSL pin high), control pins set
register defaults upon power-up or reset. The
78P2351R can then be configured via the 4-wire
serial control interface. See Pin Descriptions
section for more information.
REFERENCE CLOCK
The 78P2351R requires a reference clock supplied
to the CKREFP/N pins. For reference frequencies of
19.44MHz or 77.76MHz, the device accepts a single
ended CMOS level input at CKREFP (CKREFN tied
to ground). For reference frequency of 155.52MHz,
the device accepts a differential LVPECL clock input
at CKREFP/N. The frequency of this reference input
is selected by either the CKSL control pin or register
bit as follows:
CKSL pin
Low
Float
High
CKSL[1:0] bits
00
10
11
Reference
Frequency
19.44MHz
77.76MHz
155.52MHz
The outputs of the data comparators are connected
to the clock recovery circuits. The clock recovery
system employs a digital PLL, which utilizes a line-
rate reference frequency derived from the clock
applied to the CKREFP/N pins. After the clock and
data have been recovered, the data is converted to
binary by the CMI decoder. NRZ data is transmitted
through LVPECL drivers at the SODP/N pins.
Receiver Monitor Mode
The SCK_MON pin or MON register bit puts the
receiver in monitor mode and adds approximately
20dB of flat gain to the receive signal before
equalization. Rx Monitor Mode can handle 20dB of
flat loss typical of monitoring points with up to 6dB of
cable loss. Note that Loss of Signal detection is
disabled during Rx Monitor Mode.
Loss of Signal Detect
The 78P2351R includes an ITU-T G.783 compliant
Loss of Signal (LOS) detector. When the received
signal is less than approximately 18dB below
nominal for 80 UI, the LOS pin is asserted. The
LOS signal is cleared when the received signal is
greater than approximately 17dB below nominal for
80 UI. During LOS conditions, the receive data
outputs are squelched and held at logic ‘0’.
Note:
Loss of Signal detection is disabled during
Local Loopback and Receive Monitor Modes.
TRANSMITTER OPERATION
The transmitter section generates an adjustable
G.703 compliant analog signal for transmission
through a center-tapped transformer onto 75Ω
coaxial cable. Serial NRZ data is input to the
78P2351R on the SIDP/N pins at LVPECL levels
and passed to a low jitter clock and data recovery
circuit.
An optional clock decoupling FIFO is
provided to decouple the on chip and off chip clocks.
The NRZ data is encoded to CMI to ensure an
adequate number of transitions.
Each of the transmit timing modes can be configured
in HW mode or SW mode as shown in the table
below.
Tx Mode
Reserved
Synchronous
(FIFO enabled)
Plesiochronous
Loop-timing
RECEIVER OPERATION
The receiver accepts G.703 compliant CMI encoded
data at 155.52Mbit/s from the RXP/N inputs. When
transformer-coupled to the line, the receiver can
handle over 15dB of cable loss. The receive jitter
tolerance is compliant with all relevant standards
even with 12.7dB worth of cable attenuation and
inter-symbol interference (ISI). See Receiver Jitter
Tolerance section for more info.
The CMI signal first enters an AGC and a high
performance adaptive equalizer designed to
overcome inter-symbol interference caused by long
cable lengths. The variable gain differential amplifier
automatically controls the gain to maintain a
constant voltage level output regardless of the input
voltage level.
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HW Control
CKMODE
Low
Floating
High
n/a
SW Control
SMOD[1:0]
00
10
01
11
78P2351R 155Mbps NRZ to CMI Converter
Plesiochronous Mode
Plesiochronous mode represents a common
condition where the transmit data is not source
synchronous to the reference clock input (i.e. local
crystal oscillator, external loopback). In this mode,
the 78P2351R will recover the clock from the serial
plesiochronous NRZ transmit data and bypass the
internal FIFO.
System
Clock
XO
CKREFP
Clock Synthesizer
The transmit clock synthesizer is a low-jitter PLL that
generates a 311.04 MHz clock for the CMI encoder.
A synthesized 155.52 MHz reference clock is also
used in both the receive and transmit sides for clock
and data recovery.
Pulse Amplitude Adjustment
Controls for adjusting the transmit pulse amplitude
are provided in both hardware and software modes.
Amplitude boosts of 5% and 10% can be enabled by
the TXOUT0 pin or BST[1:0] register bits as follows:
TXOUT0 pin
BST[1:0] bits
00
01
11
Amplitude
Normal
5% boost
10% boost
Low
Float
High
NRZ
SIDP/N
CMIP/N
CMI
XFMR
Coax
Framer/
Mapper
NRZ
TDK
78P2351R
SODP/N
RXP/N
CMI
XFMR
Coax
Figure 1: Plesiochronous Mode
Synchronous Mode
When the NRZ transmit data is source synchronous
with the reference clock applied at CKREFP/N as
shown in Figure 2, the 78P2351R can be optionally
used in synchronous mode or re-timing mode. In
this mode, the 78P2351R will recover the clock from
the serial NRZ data input and pass the data through
an integrated FIFO.
System Reference Clock
Transmit Backplane Equalizer
An optional fixed equalizer is integrated in the
transmit path for architectures that use LIUs on
active interface cards. The fixed equalizer can
compensate for up to 1.5m of trace and can be
enabled by the TXOUT1 pin or TXEQ bit as follows:
TXOUT1 pin
Low
Float
TXEQ bit
1
0
Tx Equalizer
Enabled
Disabled
CKREFP/N
POWER-DOWN FUNCTION
CMIP/N
NRZ
SIDP/N
CMI
XFMR
Coax
Framer/
Mapper
NRZ
TDK
78P2351R
SODP/N
RXP/N
CMI
XFMR
Coax
Power-down control is provided to allow the
78P2351R to be shut off. Transmit and receive
power-down can be set independently through SW
control.
Global power-down is achieved by
powering down both the transmitter and receiver.
Note:
the serial interface and configuration
registers are not affected by power-down.
The transmitter can also be powered down using the
TXPD control pin. The CMI outputs are tri-stated
during transmit power-down for redundancy
applications.
The TXPD pin is active in both
hardware and software modes.
Figure 2: Synchronous
Since the reference clock and transmit clock/data go
through different delay paths, it is inevitable that the
phase relationship between the two clocks can vary
in a bounded manner due to the fact that the
absolute delays in the two paths can vary over time.
The FIFO allows long-term clock phase drift, not
exceeding +/- 25.6ns, to be handled without transmit
error. If the clock wander exceeds the specified
limits, the FIFO will over or under flow, and the
FERR register signal will be asserted. The FIFO is
re-centered by asserting the FRST bit. Note that the
FIFO is also automatically re-centered when the
TXLOL register bit (Transmit Loss of Lock)
transitions from high to low.
Note:
External remote loopbacks (i.e. loopback
within framer) are not possible in synchronous
operation (FIFO enabled) unless the reference
clock is synchronous with the recovered receive
clock (loop-timing).
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