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CY2DP1504
1:4 LVPECL Fanout Buffer
with Selectable Clock Input
Features
■
■
■
■
■
■
■
■
■
Functional Description
The CY2DP1504 is an ultra-low noise, low-skew,
low-propagation delay 1:4 LVPECL fanout buffer targeted to
meet the requirements of high-speed clock distribution
applications. The CY2DP1504 can select between two separate
LVPECL input clock pairs using the IN_SEL pin. The
synchronous clock enable function ensures glitch-free output
transitions during enable and disable periods. The device has a
fully differential internal architecture that is optimized to achieve
low additive jitter and low skew at operating frequencies of up to
1.5 GHz.
Select one of two low-voltage positive emitter-coupled logic
(LVPECL) input pairs to distribute to four LVPECL output pairs
30 ps maximum output-to-output skew
480-ps maximum propagation delay
0.15-ps maximum additive RMS phase jitter at 156.25 MHz
(12-kHz to 20-MHz offset)
Up to 1.5-GHz operation
Synchronous clock enable function
20-pin thin shrunk small outline package (TSSOP)
2.5-V or 3.3-V operating voltage
[1]
Commercial and industrial operating temperature range
Logic Block Diagram
V
DD
V
SS
IN0
IN0#
IN1
IN1#
IN_SEL
100k
Q0
Q0#
Q1
Q1#
Q2
Q2#
Q3
Q3#
V
DD
100k
Q
D
CLK_EN
Note
1. Input AC-coupling capacitors are required for voltage-translation applications.
Cypress Semiconductor Corporation
Document Number: 001-56215 Rev. *F
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised January 10, 2011
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CY2DP1504
Contents
Pinouts .............................................................................. 3
Absolute Maximum Ratings ............................................ 4
Operating Conditions....................................................... 4
DC Electrical Specifications ............................................ 5
AC Electrical Specifications ............................................ 6
Ordering Information...................................................... 10
Ordering Code Definition ........................................... 10
Package Dimension........................................................ 11
Acronyms ........................................................................ 12
Document Conventions ................................................. 12
Document History Page ................................................. 13
Sales, Solutions, and Legal Information ...................... 14
Worldwide Sales and Design Support ....................... 14
Products .................................................................... 14
PSoC Solutions ......................................................... 14
Document Number: 001-56215 Rev. *F
Page 2 of 14
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CY2DP1504
Pinouts
Figure 1. Pin Diagram – 20-Pin TSSOP Package
V
SS
CLK_EN
IN_SEL
IN0
IN0#
IN1
IN1#
NC
NC
V
DD
1
2
3
4
5
6
7
8
9
10
CY2DP1504
20
19
18
17
16
15
14
13
12
11
Q0
Q0#
V
DD
Q1
Q1#
Q2
Q2#
V
DD
Q3
Q3#
Table 1. Pin Definitions
Pin No.
1
2
Pin Name
V
SS
CLK_EN
Input
Pin Type
Power
Ground
Synchronous clock enable. Low-voltage complementary metal oxide
semiconductor (LVCMOS)/low-voltage transistor-transistor-logic (LVTTL).
When CLK_EN = Low, Q(0:3) outputs are held Low and Q(0:3)# outputs
are held High
Input clock select pin. LVCMOS/LVTTL;
When IN_SEL = Low, the IN0/IN0# differential input pair is active
When IN_SEL = High, the IN1/IN1# differential input pair is active
LVPECL input clock. Active when IN_SEL = Low
LVPECL complementary input clock. Active when IN_SEL = Low
LVPECL input clock. Active when IN_SEL = High
LVPECL complementary input clock. Active when IN_SEL = High
No connection
Power
Output
Output
Power supply
LVPECL complementary output clocks
LVPECL output clocks
Description
3
IN_SEL
Input
4
5
6
7
8,9
10,13,18
11,14,16,19
12,15,17,20
IN0
IN0#
IN1
IN1#
NC
V
DD
Q(0:3)#
Q(0:3)
Input
Input
Input
Input
Document Number: 001-56215 Rev. *F
Page 3 of 14
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CY2DP1504
Absolute Maximum Ratings
Parameter
V
DD
V
IN[2]
V
OUT[2]
T
S
ESD
HBM
L
U
UL–94
MSL
Supply voltage
Input voltage, relative to V
SS
DC output or I/O voltage, relative to V
SS
Storage temperature
Electrostatic discharge (ESD) protection
(Human body model)
Latch up
Flammability rating
Moisture sensitivity level
At 1/8 in
Description
Condition
Nonfunctional
Nonfunctional
Nonfunctional
Non functional
JEDEC STD 22-A114-B
Min
–0.5
–0.5
–0.5
–55
2000
Max
4.6
lesser of 4.0
or V
DD
+ 0.4
lesser of 4.0
or V
DD
+ 0.4
Unit
V
V
V
°C
V
150
–
Meets or exceeds JEDEC Spec
JESD78B IC Latchup Test
V-0
3
Operating Conditions
Parameter
V
DD
T
A
t
PU
Supply voltage
Ambient operating temperature
Power ramp time
Description
Condition
2.5-V supply
3.3-V supply
Commercial
Industrial
Power-up time for V
DD
to reach
minimum specified voltage (power
ramp must be monotonic).
Min
2.375
3.135
0
–40
0.05
Max
2.625
3.465
70
85
500
Unit
V
V
°C
°C
ms
Note
2. The voltage on any I/O pin cannot exceed the power pin during power up. Power supply sequencing is not required.
Document Number: 001-56215 Rev. *F
Page 4 of 14
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