CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
256K x 36/512K x 18 Synchronous
Pipelined SRAM
Features
• Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns
• Fast clock speed: 225 MHz, 200 MHz, 166 MHz, and 150
MHz
• Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns
• Optimal for performance (two cycle chip deselect,
depth expansion without wait state)
• 3.3V –5% and +10% power supply
• 3.3V or 2.5V I/O supply
• 5V tolerant inputs except I/Os
• Clamp diodes to V
SS
at all inputs and outputs
• Common data inputs and data outputs
• Byte Write Enable and Global Write control
• Multiple chip enables for depth expansion:
three chip enables for TA(GVTI)/A(CY) package version
and two chip enables for B(GVTI)/BG(CY) and
T(GVTI)/AJ(CY) package versions
• Address pipeline capability
• Address, data and control registers
• Internally self-timed Write Cycle
• Burst control pins (interleaved or linear burst
sequence)
• Automatic power-down feature available using ZZ
mode or CE select.
• JTAG boundary scan for B/BG and T/AJ package
version
• Low profile 119-bump, 14-mm x 22-mm PBGA (Ball Grid
Array) and 100-pin TQFP packages
The
CY7C1366A/GVT71256C36
and
CY7C1367A/
GVT71512C18 SRAMs integrate 262,144 x 36 and 524,288 x
18 SRAM cells with advanced synchronous peripheral circuitry
and a 2-bit counter for internal burst operation. All
synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (CLK). The synchronous
inputs include all addresses, all data inputs, address-pipelining
Chip Enable (CE), depth-expansion Chip Enables (CE
2
and
CE
3
), Burst Control Inputs (ADSC, ADSP, and ADV), Write
Enables (BWa, BWb, BWc, BWd, and BWE), and Global Write
(GW). However, the CE
3
Chip Enable input is only available
for the TA(GVTI)/A(CY) package version.
Asynchronous inputs include the Output Enable (OE) and
Burst Mode Control (MODE). The data outputs (Q), enabled
by OE, are also asynchronous.
Addresses and chip enables are registered with either
Address Status Processor (ADSP) or Address Status
Controller (ADSC) input pins. Subsequent burst addresses
can be internally generated as controlled by the Burst Advance
Pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed WRITE cycle. WRITE cycles can be one
to four bytes wide, as controlled by the write control inputs.
Individual byte write allows an individual byte to be written.
BWa controls DQa. BWb controls DQb. BWc controls DQc.
BWd controls DQd. BWa, BWb, BWc, and BWd can be active
only with BWE being LOW. GW being LOW causes all bytes
to be written. The x18 version only has 18 data inputs/outputs
(DQa and DQb) along with BWa and BWb (no BWc, BWd,
DQc, and DQd).
For the B(GVTI)/BG(CY) and T(GVTI)/AJ(CY) package
versions, four pins are used to implement JTAG test capabil-
ities: Test Mode Select (TMS), Test Data-In (TDI), Test Clock
(TCK), and Test Data-Out (TDO). The JTAG circuitry is used
to serially shift data to and from the device. JTAG inputs use
LVTTL/LVCMOS levels to shift data during this testing mode
of operation. The TA package version does not offer the JTAG
capability.
The
CY7C1366A/GVT71256C36
and
CY7C1367A/
GVT71512C18 operate from a +3.3V power supply. All inputs
and outputs are LVTTL compatible.
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low power CMOS designs using advanced
triple-layer polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two high valued
resistors.
Selection Guide
7C1366A-225/
71256C36-4.4
7C1367A-225/
71512C18-4.4
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
2.5
570
10
7C1366A-200/
71256C36-5
7C1367A-200/
71512C18-5
3.0
510
10
7C1366A-166/
71256C36-6
7C1367A-166/
71512C18-6
3.5
425
10
7C1366A-150/
71256C36-6.7
7C1367A-150/
71512C18-6.7
3.5
380
10
Unit
ns
mA
mA
Cypress Semiconductor Corporation
Document #: 38-05264 Rev. *A
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised March 17, 2003
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
256K × 36 Pin Descriptions
X36 PBGA Pins
X36 QFP Pins
Name
A0
A1
A
Type
Description
4P
37
4N
36
2A, 3A, 5A, 6A, 3B, 35, 34, 33, 32,
5B, 6B, 2C, 3C, 5C, 100, 99, 82, 81,
6C, 2R, 6R, 3T, 4T, 44, 45, 46, 47, 48,
5T
49, 50
92 (T/AJ Version)
43 (TA/A Version)
5L
5G
3G
3L
4M
93
94
95
96
87
Input-
Addresses:
These inputs are registered and must meet the set
Synchronous up and hold times around the rising edge of CLK. The burst
counter generates internal addresses associated with A0 and A1,
during burst cycle and wait cycle.
BWa
BWb
BWc
BWd
BWE
Input-
Byte Write:
A byte write is LOW for a WRITE cycle and HIGH for
Synchronous a READ cycle. BWa controls DQa. BWb controls DQb. BWc
controls DQc. BWd controls DQd. Data I/O are high impedance
if either of these inputs are LOW, conditioned by BWE being
LOW.
Input-
Write Enable:
This active LOW input gates byte write operations
Synchronous and must meet the set-up and hold times around the rising edge
of CLK.
Input-
Global Write:
This active LOW input allows a full 36-bit Write to
Synchronous occur independent of the BWE and BWn lines and must meet the
set-up and hold times around the rising edge of CLK.
Input-
Clock:
This signal registers the addresses, data, chip enables,
Synchronous write control, and burst control inputs on its rising edge. All
synchronous inputs must meet set up and hold times around the
clock’s rising edge.
Input-
Chip Enable:
This active LOW input is used to enable the device
Synchronous and to gate ADSP.
Input-
Chip Enable:
This active HIGH input is used to enable the
Synchronous device.
Input-
Chip Enable:
This active LOW input is used to enable the device.
Synchronous Not available for B and T package versions.
Input
Output Enable:
This active LOW asynchronous input enables
the data output drivers.
4H
88
GW
4K
89
CLK
4E
2B
(not available for
PBGA)
4F
4G
98
97
92 (for TA/A
Version only)
86
83
CE
1
CE
2
CE
3
OE
ADV
Input-
Address Advance:
This active LOW input is used to control the
Synchronous internal burst counter. A HIGH on this pin generates wait cycle
(no address advance).
Input-
Address Status Processor:
This active LOW input, along with
Synchronous CE being LOW, causes a new external address to be registered
and a READ cycle is initiated using the new address.
Input-
Address Status Controller:
This active LOW input causes
Synchronous device to be deselected or selected along with new external
address to be registered. A Read or Write cycle is initiated
depending upon write control inputs.
Input-
Static
Mode:
This input selects the burst sequence. A LOW on this pin
selects Linear Burst. A NC or HIGH on this pin selects Interleaved
Burst.
4A
84
ADSP
4B
85
ADSC
3R
31
MOD
E
ZZ
7T
64
Input-
Sleep:
This active HIGH input puts the device in low power
Asynchronous consumption standby mode. For normal operation, this input has
to be either LOW or NC (No Connect).
Input/
Output
Data Inputs/Outputs:
First Byte is DQa. Second Byte is DQb.
Third Byte is DQc. Fourth Byte is DQd. Input data must meet
set-up and hold times around the rising edge of CLK.
(a) 6P, 7P, 7N, 6N,
6M, 6L, 7L, 6K, 7K,
(b) 7H, 6H, 7G, 6G,
6F, 6E, 7E, 7D, 6D,
(c) 2D, 1D, 1E, 2E,
2F, 1G, 2G, 1H, 2H,
(d) 1K, 2K, 1L, 2L,
2M, 1N, 2N, 1P, 2P
(a) 51, 52, 53, 56,
57, 58, 59, 62, 63
(b) 68, 69, 72, 73,
74, 75, 78, 79, 80
(c) 1, 2, 3, 6, 7, 8,
9, 12, 13
(d) 18, 19, 22, 23,
24, 25, 28, 29, 30
DQa
DQb
DQc
DQd
Document #: 38-05264 Rev. *A
Page 5 of 29
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