CY2V014
LVPECL Voltage Controlled
Crystal Oscillator (VCXO)
Features
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Benefits
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High-frequency VCXO with LVPECL output
Any output frequency from 50 MHz to 690 MHz
Available either factory configured or field programmable
Integrated phase-locked loop (PLL)
1 ps typical RMS Phase Jitter
Output Enable or Power-down function
Supply voltage: 3.3 V or 2.5 V
Pb-free package: 5.0 × 3.2 mm LCC
Commercial and industrial temperature ranges
Eliminates the need for external crystal
Low-noise internal PLL
Fast time to market
Suitable for HDDs, consumer and networking applications
Small footprint
Application compatibility in standard and low-power systems
Field-programmable for reduced inventory
Logic Block Diagram
Crystal
Oscillator
Low Noise
PLL
4
PROGRAMMABLE
CONFIGURATION
1
VIN
2
Pull-up
OE/PD#
OUTPUT
DIVIDER
CLK
5
CLK#
6
VDD
3
VSS
Cypress Semiconductor Corporation
Document #: 001-06458 Rev. *B
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised December 2, 2010
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CY2V014
Pinouts
Figure 1. 6-Pin Ceramic LCC
VIN 1
OE/PD# 2
VSS 3
6 VDD
5 CLK#
4 CLK
Pin Definitions
Pin
1
2
V
IN
OE/PD#
Name
I/O Type
Analog Input
CMOS Input, internal
pull-up
Power
Output
Power
Description
VCXO control voltage. Positive slope.
Output Enable pin: Active HIGH. If OE = 1, CLK is enabled.
Power-down pin: Active LOW. If PD# = 0, Power-down is enabled.
The functionality of this pin is programmable.
Power supply ground
Clock output. LVPECL outputs. CLK# is the complement of CLK.
Positive power supply: 2.5 V or 3.3 V
3
4, 5
6
V
SS
CLK, CLK#
V
DD
Functional Description
The CY2V014 is a high-performance high-frequency
voltage-controlled crystal oscillator (VCXO).
The device uses a Cypress proprietary low-noise PLL to
synthesize the frequency from an embedded crystal.
The output frequency is user adjustable by means of an analog
control voltage applied to the V
IN
pin.
Factory-Configured CY2V014
For customers wanting ready-to-use devices, the CY2V014 is
available factory-configured, with no programming required. All
requests must be submitted to the local Cypress Field Appli-
cation Engineer (FAE) or sales representative. Once the request
has been processed, you will receive a new part number,
samples, and data sheet with the programmed values. This part
number will be used for additional sample requests and
production orders.
VCXO Control Voltage (V
IN
, pin 1)
V
IN
is an analog input that is used to adjust the output frequency.
The nominal output frequency is defined when V
IN
= V
DD
/2.
Increasing the voltage on V
IN
increases the output frequency,
while decreasing the voltage on V
IN
decreases the output
frequency. Any voltage between V
SS
and V
DD
is allowed on V
IN
.
The voltage/frequency slope is very linear over most of the
control voltage range.
Programming Variables
Output Frequency
Any frequency between 50 MHz and 690 MHz may be specified.
Absolute Pull Range
The absolute pull range (APR) may be specified.
Programming Description
Field-Programmable CY2V014
Field-programmable devices are shipped unprogrammed, and
must be programmed before use. Customers can use Cyber-
Clocks™ Online Software to specify the device configuration and
generate a .JED programming file. Programming of samples and
prototype quantities is available using the CY3672 programmer.
Third-party vendors manufacture programmers for small to large
volume applications. Cypress’s value-added distribution
partners also provide programming services. Field-program-
mable devices are designated with an “F” in the part number, and
are intended for quick prototyping and inventory reduction.
Pin 2: Output Enable or Power-Down (OE/PD#)
Pin 2 can be programmed as either output enable (OE) or
Power-down (PD#). The OE function is used to enable or disable
the CLK output very quickly, but it does not reduce core power
consumption. The PD# function puts the device into a low-power
state, but wake-up takes longer because the PLL must reacquire
lock.
Document #: 001-06458 Rev. *B
Page 2 of 9
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CY2V014
Absolute Maximum Conditions
Parameter
V
CC
V
IN
T
S
T
J
ESD
HBM
UL–94
MSL
Description
Supply Voltage
Input Voltage
Temperature, Storage
Temperature, Junction
ESD Protection (Human Body Model) MIL-STD-883, Method 3015
Flammability Rating
Moisture Sensitivity Level
At 1/8 in.
Relative to V
SS
Non Functional
Condition
Min
–0.5
–0.5
–55
–40
2000
V–0
1
Max
4.4
V
DD
+0.5
150
125
Unit
V
VDC
°C
°C
V
Note: The voltage on any input or I/O pin cannot exceed the power pin during power-up.
Operating Conditions
Parameter
V
DD
T
PU
T
A
T
A
Supply Voltage Range
Power-up Time for V
DD
to Reach Minimum Specified Voltage (power ramp
must be monotonic)
Ambient Temperature (Commercial)
Ambient Temperature (Industrial)
Description
Min
3.0
2.25
0.05
0
–40
Typ
3.3
2.5
–
–
–
Max
3.6
2.75
500
70
85
Unit
V
ms
°C
°C
DC Electrical Characteristics
Parameter
V
OH
V
OL
V
OD1
V
OD2
V
OCM
V
IH
V
IL
R
UP
I
IH
I
IL
V
VIN
I
IVIN
L
IN
I
OZ
I
DD
I
SB
Description
LVPECL High Output Voltage
LVPECL Low Output Voltage
LVPECL Output Voltage Swing
(V
OH
– V
OL
)
LVPECL Output Voltage Swing
(V
OH
– V
OL
)
LVPECL Output Common Mode
Voltage (V
OH
+ V
OL
)/2
CMOS Input High Voltage
CMOS Input Low Voltage
Internal Pull-up Resistor
CMOS Input High Current
CMOS Input Low Current
V
IN
Input Voltage
V
IN
Input Current
V
IN
to f
OUT
Linearity
Output Leakage Current
Operating Supply Current
Standby Supply Current
V
SS
≤
V
IN
≤
V
DD
0.2 × V
DD
≤
V
IN
≤
0.8 × V
DD
Three-state output, PD#/OE = V
SS
V
DD
= 3.3 V or 2.5 V, CLK = 150 MHz,
C
LOAD
= 0, PD#/OE = V
DD
PD# = V
SS
V
IN
= V
DD
V
IN
= V
SS
Condition
Min
Typ
–
–
–
–
–
–
–
100
–
–
–
–
1
–
–
–
Max
V
DD
–
0.75
V
DD
–
1.625
1000
1000
–
–
0.3 × V
DD
–
10
120
V
DD
10
–
35
100
1
Unit
V
V
mV
mV
V
V
V
kΩ
μA
μA
V
μA
%
μA
mA
mA
V
DD
= 3.3 V or 2.5 V, R
TERM
= 50
Ω
to V
DD
– 1.15
V
DD
– 2.0 V
V
DD
= 3.3 V or 2.5 V, R
TERM
= 50
Ω
to V
DD
– 2.0
V
DD
– 2.0 V
V
DD
= 3.3 V or 2.5 V, R
TERM
= 50
Ω
to
V
DD
– 2.0 V
V
DD
= 2.5 V, R
TERM
= 50
Ω
to V
DD
–
1.4 V
V
DD
= 2.5 V, R
TERM
= 50
Ω
to V
DD
–
1.4 V
600
500
1.2
0.7 × V
DD
–
–
–
–
0
–
–
–35
–
–
Document #: 001-06458 Rev. *B
Page 3 of 9
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CY2V014
AC Electrical Characteristics
Parameter
f
OUT
FS
FACT
FS
FIELD
APR
Description
Output Frequency
Frequency Stability – factory
programmed devices
V
IN
= V
DD
/2
[1]
Condition
Min
50
–60
–100
±100
±50
10
45
–
–
–
–
Typ
–
–
–
–
–
–
50
350
_
–
–
Max
690
60
100
–
–
–
55
–
100
100
10
Unit
MHz
ppm
ppm
ppm
Frequency Stability – field program- V
IN
= V
DD
/2
[1]
mable devices
Absolute Pull Range
V
IN
= V
DD
to V
SS
, relative to nominal
f
OUT
, across operating temperature and
voltage range
[2]
–3 dB
Measured at zero crossing
20% and 80% of full output swing
Time from falling edge on OE to stopped
outputs (Asynchronous)
Time from rising edge on OE to outputs
at a valid frequency (Asynchronous)
Time for CLK to reach valid frequency
measured from the time V
DD
=
V
DD
(Min) or from PD# rising edge.
f
OUT
= 106.25 MHz (12 kHz–20 MHz)
f
OUT
= 106.25 MHz
BW
DC
T
R
, T
F
T
OE1
T
OE2
T
LOCK
Modulation Bandwidth (V
IN
)
Output Duty Cycle
Output Rise and Fall Time
Output Disable Time
Output Enable Time
Start-up Time
kHz
%
ps
ns
ns
ms
T
J1
T
J2
RMS Phase Jitter
Peak-to-peak Period Jitter
–
–
1
30
–
–
ps
ps
Notes
1. Frequency stability is the maximum variation in frequency from F
0
. It includes initial accuracy, plus variation from temperature, supply voltage, shock, vibration
and first year aging.
2. APR is the minimum pull range under all conditions over the device lifetime, including aging for 10 years. APR is relative to F
0.
Document #: 001-06458 Rev. *B
Page 4 of 9
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CY2V014
Switching Waveforms
Figure 2. Duty Cycle Timing (DC = t
1A
/t
1B
)
CLK
t
1A
t
1B
Figure 3. Output Differential Voltage
CLK
V
OD
CLK#
V
A
V
OCM
= (V
A
+ V
B
)/2
V
B
Figure 4. Output Rise/Fall Time
steady state high
CLK, CLK#
steady state low
Tr
Tf
Output Rise time (Tr) =20 to 80% of full output swing
Output Fall time (Tf) = 80 to 20% of full output swing
Figure 5. Output Enable/Disable Timing
OE / PD#
V
IL
V
IH
T
OE2
CLK
T
OE1
High Impedance
Termination Circuits
Figure 6. LVPECL Termination
VDD - 2V
(VDD = 3.3V)
50Ω
50Ω
VDD - 2V or 1.4V
(VDD = 2.5V)
50Ω
50Ω
CLK
BUF
50Ω
50Ω
CLK
BUF
50Ω
50Ω
CLK#
CLK#
Document #: 001-06458 Rev. *B
Page 5 of 9
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