SN54BCT8240A, SN74BCT8240A
SCAN TEST DEVICES
WITH OCTAL INVERTING BUFFERS
SCBS067E – FEBRUARY 1990 – REVISED DECEMBER 1996
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Members of the Texas Instruments
SCOPE
™
Family of Testability Products
Octal Test-Integrated Circuits
Functionally Equivalent to ’F240 and
’BCT240 in the Normal-Function Mode
Compatible With the IEEE Standard
1149.1-1990 (JTAG) Test Access Port and
Boundary-Scan Architecture
Test Operation Synchronous to Test
Access Port (TAP)
Implement Optional Test Reset Signal by
Recognizing a Double-High-Level Voltage
(10 V ) on TMS Pin
SCOPE
™
Instruction Set
– IEEE Standard 1149.1-1990 Required
Instructions, Optional INTEST, CLAMP,
and HIGHZ
– Parallel-Signature Analysis at Inputs
– Pseudo-Random Pattern Generation
From Outputs
– Sample Inputs/Toggle Outputs
Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic
and Ceramic 300-mil DIPs (JT, NT)
SN54BCT8240A . . . JT PACKAGE
SN74BCT8240A . . . DW OR NT PACKAGE
(TOP VIEW)
1OE
1Y1
1Y2
1Y3
1Y4
GND
2Y1
2Y2
2Y3
2Y4
TDO
TMS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
2OE
1A1
1A2
1A3
1A4
2A1
V
CC
2A2
2A3
2A4
TDI
TCK
SN54BCT8240A . . . FK PACKAGE
(TOP VIEW)
description
The ’BCT8240A scan test devices with octal
buffers are members of the Texas Instruments
SCOPE™ testability integrated-circuit family. This
family of devices supports IEEE Standard
1149.1-1990 boundary scan to facilitate testing of
complex circuit-board assemblies. Scan access
to the test circuitry is accomplished via the 4-wire
test access port (TAP) interface.
1A2
1A1
2OE
NC
1OE
1Y1
1Y2
5
6
7
8
9
1A3
1A4
2A1
NC
V
CC
2A2
2A3
4
3 2 1 28 27 26
25
24
23
22
21
20
10
11
19
12 13 14 15 16 17 18
2A4
TDI
TCK
NC
TMS
TDO
2Y4
NC – No internal connection
In the normal mode, these devices are functionally equivalent to the ’F240 and ’BCT240 octal buffers. The test
circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device terminals
or to perform a self test on the boundary-test cells. Activating the TAP in normal mode does not affect the
functional operation of the SCOPE™ octal buffers.
In the test mode, the normal operation of the SCOPE™ octal buffers is inhibited and the test circuitry is enabled
to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform
boundary-scan test operations, as described in IEEE Standard 1149.1-1990.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SCOPE is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1Y3
1Y4
GND
NC
2Y1
2Y2
2Y3
Copyright
©
1996, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1
SN54BCT8240A, SN74BCT8240A
SCAN TEST DEVICES
WITH OCTAL INVERTING BUFFERS
SCBS067E – FEBRUARY 1990 – REVISED DECEMBER 1996
description (continued)
Four dedicated test terminals control the operation of the test circuitry: test data input (TDI), test data output
(TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing
functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation
(PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.
The SN54BCT8240A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74BCT8240A is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
(normal mode, each buffer)
INPUTS
OE
H
L
L
A
X
L
H
OUTPUT
Y
Z
H
L
logic symbol
†
Φ
SCAN
’BCT8240A
TDI
TMS
TCK-IN
TCK-OUT
1OE
2OE
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
23
22
21
20
19
17
16
15
2
1
1
24
EN1
EN2
2
3
4
5
7
8
9
10
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
TDO
11
TDO
TDI
TMS
TCK
14
12
13
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DW, JT, and NT packages.
2
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DALLAS, TEXAS 75265
SN54BCT8240A, SN74BCT8240A
SCAN TEST DEVICES
WITH OCTAL INVERTING BUFFERS
SCBS067E – FEBRUARY 1990 – REVISED DECEMBER 1996
functional block diagram
VCC
1OE
1
Boundary-Scan Register
VCC
1A1
23
2
1Y1
One of Four Channels
VCC
2OE
24
VCC
2A1
19
7
2Y1
One of Four Channels
Bypass Register
Boundary- Control
Register
VCC
TDI
14
VCC
TMS
12
VCC
TCK
13
TAP
Controller
Instruction Register
VCC
11
TDO
Pin numbers shown are for the DW, JT, and NT packages.
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SN54BCT8240A, SN74BCT8240A
SCAN TEST DEVICES
WITH OCTAL INVERTING BUFFERS
SCBS067E – FEBRUARY 1990 – REVISED DECEMBER 1996
Terminal Functions
TERMINAL
NAME
1A1–1A4,
2A1–2A4
GND
1OE, 2OE
DESCRIPTION
Normal-function data inputs. See function table for normal-mode logic. Internal pullups force these inputs to a high level if
left unconnected.
Ground
Normal-function output-enable inputs. See function table for normal-mode logic. Internal pullups force these inputs to a high
level if left unconnected.
Test clock. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the device are synchronous to
TCK. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK. An internal pullup forces
TCK to a high level if left unconnected.
Test data input. One of four terminals required by IEEE Standard 1149.1-1990. TDI is the serial input for shifting data through
the instruction register or selected data register. An internal pullup forces TDI to a high level if left unconnected.
Test data output. One of four terminals required by IEEE Standard 1149.1-1990. TDO is the serial output for shifting data
through the instruction register or selected data register. An internal pullup forces TDO to a high level when it is not active
and is not driven from an external source.
Test mode select. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the device through its
TAP-controller states. An internal pullup forces TMS to a high level if left unconnected. TMS also provides the optional test
reset signal of IEEE Standard 1149.1-1990. This is implemented by recognizing a third logic level, double high (VIHH), at TMS.
Supply voltage
Normal-function data outputs. See function table for normal-mode logic.
TCK
TDI
TDO
TMS
VCC
1Y1–1Y4,
2Y1–2Y4
4
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DALLAS, TEXAS 75265
SN54BCT8240A, SN74BCT8240A
SCAN TEST DEVICES
WITH OCTAL INVERTING BUFFERS
SCBS067E – FEBRUARY 1990 – REVISED DECEMBER 1996
test architecture
Serial-test information is conveyed by means of a 4-wire test bus, or TAP, that conforms to IEEE Standard
1149.1-1990. Test instructions, test data, and test control signals all are passed along this serial-test bus. The
TAP controller monitors two signals from the test bus, TCK and TMS. The TAP controller extracts the
synchronization (TCK) and state control (TMS) signals from the test bus and generates the appropriate on-chip
control signals for the test structures in the device. Figure 1 shows the TAP-controller state diagram.
The TAP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK, and
output data changes on the falling edge of TCK. This scheme ensures that data to be captured is valid for fully
one-half of the TCK cycle.
The functional block diagram shows the IEEE Standard 1149.1-1990 4-wire test bus and boundary-scan
architecture and the relationship among the test bus, the TAP controller, and the test registers. As shown, the
device contains an 8-bit instruction register and three test-data registers: an 18-bit boundary-scan register, a
2-bit boundary-control register, and a 1-bit bypass register.
Test-Logic-Reset
TMS = H
TMS = L
TMS = H
Run-Test/Idle
TMS = L
Select-DR-Scan
TMS = L
TMS = H
Capture-DR
TMS = L
Shift-DR
TMS = L
TMS = H
TMS = H
Exit1-DR
TMS = L
Pause-DR
TMS = L
TMS = H
TMS = L
Exit2-DR
TMS = H
Update-DR
TMS = H
TMS = L
TMS = L
Exit2-IR
TMS = H
Update-IR
TMS = H
TMS = L
TMS = H
Exit1-IR
TMS = L
Pause-IR
TMS = L
TMS = H
TMS = H
TMS = H
Capture-IR
TMS = L
Shift-IR
TMS = L
TMS = H
Select-IR-Scan
TMS = L
TMS = H
Figure 1. TAP-Controller State Diagram
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