5
PRELIMINARY
CY7C1354V25
CY7C1356V25
256Kx36/512Kx18 Pipelined SRAM with NoBL™ Architecture
Features
•
Pin compatible and functionally equivalent to ZBT
• Supports 200-MHz bus operations with zero wait states
— Data is transferred on every clock
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Fully Registered (inputs and outputs) for pipelined op-
eration
• Byte Write capability
• Common I/O architecture
• Single 2.5V power supply
• Fast clock-to-output times
— 3.2 ns (for 200-MHz device)
— 3.5 ns (for 166-MHz device)
— 4.2 ns (for 133-MHz device)
•
•
•
•
— 5.0 ns (for 100-MHz device)
Clock Enable (CEN) pin to suspend operation
Synchronous self-timed writes
Available in 100 TQFP & 119 BGA Packages
Burst Capability—linear or interleaved burst order
tively designed specifically to support unlimited true
back-to-back Read/Write operations without the insertion of
wait states. The CY7C1354V25/CY7C1356V25 is equipped
with the advanced No Bus Latency™ (NoBL) logic required
to enable consecutive Read/Write operations with data being
transferred on every clock cycle. This feature dramatically im-
proves the throughput of data through the SRAM, especially in
systems that require frequent Write/Read transitions.The
CY7C1354V25/CY7C1356V25 is pin compatible and function-
ally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock.All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal, which
when deasserted suspends operation and extends the previ-
ous clock cycle. Maximum access delay from the clock rise is
3.2 ns (200-MHz device).
Write operations are controlled by the Byte Write Selects
(BWSa-BWSd for CY7C1354V25 and BWSa-BWSb for
CY7C1356V25) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
Functional Description
The CY7C1354V25 and CY7C1356V25 are 2.5V, 256K by 36
and 512K by 18 Synchronous-Pipelined Burst SRAMs respec-
Logic Block Diagram
CLK
CE
ADV/LD
A
x
CEN
CE
1
CE2
CE3
WE
BWS
x
Mode
CONTROL
and WRITE
LOGIC
256KX36/
512KX18
MEMORY
ARRAY
OUTOUT
REGISTERS
and LOGIC
D
Data-In REG.
Q
CY7C1354
A
X
DQ
X
DP
X
BWS
X
X = 17:0
X = a, b, c, d
X = a, b, c, d
X = a, b, c, d
CY7C1356
X = 18:0
X = a, b
X = a, b
X = a, b
DQ
x
DP
x
OE
.
Selection Guide
7C1354V25-200 7C1354V25-166 7C1354V25-133 7C1354V25-100
7C1356V25-200 7C1356V25-166 7C1356V25-133 7C1356V25-100
Maximum Access Time (ns)
Maximum Operating Current (mA)
Shaded areas contain advance information.
3.2
Com’l
475
10
3.5
450
10
4.0
370
10
5.0
300
10
Maximum CMOS Standby Current (mA) Com’l
No Bus Latency and NoBL are trademarks of Cypress Semiconductor Corporation.
ZBT is a trademark of Integrated Device Technology.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
August 5, 1999
PRELIMINARY
Pin Configurations
100-Pin TQFP Packages
CY7C1354V25
CY7C1356V25
A
A
CE
1
CE
2
NC
NC
BWSb
BWSa
CE
3
V
DD
V
SS
CLK
WE
CEN
OE
ADV/LD
NC
A
A
A
CE
1
CE
2
BWSd
BWSc
BWSb
BWSa
CE
3
V
DD
V
SS
CLK
WE
CEN
OE
ADV/LD
NC
A
A
NC
NC
V
DDQ
V
SS
NC
DPa
DQa
DQa
V
SS
V
DDQ
DQa
DQa
V
SS
V
DD
V
DD
V
SS
DQa
DQa
V
DDQ
V
SS
DQa
DQa
NC
NC
V
SS
V
DDQ
NC
NC
NC
DPc
DQc
DQc
V
DDQ
A
A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
NC
NC
NC
V
DDQ
V
SS
NC
NC
DQb
DQb
V
SS
V
DDQ
DQb
DQb
V
DD
V
DD
V
DD
V
SS
DQb
DQb
V
DDQ
V
SS
DQb
DQb
DPb
NC
V
SS
V
DDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1356V25
(512K x 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
V
SS
DQc
DQc
DQc
DQc
V
SS
V
DDQ
DQc
DQc
V
DD
V
DD
V
DD
V
SS
DQd
DQd
V
DDQ
V
SS
DQd
DQd
DQd
DQd
V
SS
V
DDQ
DQd
DQd
DPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
A
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DPb
DQb
DQb
V
DDQ
V
SS
CY7C1354V25
(256K x 36)
DQb
DQb
DQb
DQb
V
SS
V
DDQ
DQb
DQb
V
SS
Vdd
V
DD
V
SS
DQa
DQa
V
DDQ
V
SS
DQa
DQa
DQa
DQa
V
SS
V
DDQ
DQa
DQa
DPa
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
MODE
A
A
A
A
A
1
A
0
DNU
DNU
V
SS
V
DD
MODE
A
A
A
A
A
1
A
0
DNU
DNU
V
SS
V
DD
DNU
DNU
A
A
A
A
A
A
A
2
DNU
DNU
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PRELIMINARY
Pin Configurations
(continued)
119-Ball Bump BGA
CY7C1354V25
CY7C1356V25
CY7C1356 - 7 x 17 BGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQb
NC
V
DDQ
NC
DQb
V
DDQ
NC
DQb
V
DDQ
DQb
NC
NC
NC
V
DDQ
2
A
CE
2
A
NC
DQb
NC
DQb
NC
V
DD
DQb
NC
DQb
NC
DPb
A
A
TMS
3
A
A
A
V
SS
V
SS
V
SS
BWSb
V
SS
V
DD
V
SS
V
SS
V
SS
V
SS
V
SS
MODE
A
TDI
4
NC
ADV/LD
V
DD
NC
CE1
OE
A
WE
V
DD
CLK
NC
CEN
A1
A0
V
DD
NC
TCK
5
A
A
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
DD
V
SS
BWSa
V
SS
V
SS
V
SS
V
SS
A
TDO
6
A
CE
3
A
DQa
NC
DQa
NC
DQa
V
DD
NC
DQa
NC
DQa
NC
A
A
NC
7
V
DDQ
NC
NC
NC
DQa
V
DDQ
DQa
NC
V
DDQ
DQa
NC
V
DDQ
NC
DPa
NC
NC
V
DDQ
CY7C1354 - 7 x 17 BGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQc
DQc
V
DDQ
DQc
DQc
V
DDQ
DQd
DQd
V
DDQ
DQd
DQd
NC
NC
V
DDQ
2
A
CE
2
A
DPc
DQc
DQc
DQc
DQc
V
DD
DQd
DQd
DQd
DQd
DPd
A
NC
TMS
3
A
A
A
V
SS
V
SS
V
SS
BWSc
V
SS
V
DD
V
SS
BWSd
V
SS
V
SS
V
SS
MODE
A
TDI
4
NC
ADV/LD
V
DD
NC
CE1
OE
A
WE
V
DD
CLK
NC
CEN
A1
A0
V
DD
A
TCK
5
A
A
A
V
SS
V
SS
V
SS
BWSb
V
SS
V
DD
V
SS
BWSa
V
SS
V
SS
V
SS
V
SS
A
TDO
6
A
CE
3
A
DPb
DQb
DQb
DQb
DQb
V
DD
DQa
DQa
DQa
DQa
DQa
A
NC
NC
7
V
DDQ
NC
NC
DQb
DQb
V
DDQ
DQb
DQb
V
DDQ
DQa
DQa
V
DDQ
DQa
DPa
NC
NC
V
DDQ
3
PRELIMINARY
Pin Definitions (100-Pin TQFP)
x18 Pin Location
37, 36, 32–35,
44–50, 80–83, 99,
100
93, 94
x36 Pin Location
37, 36, 32–35,
44–50, 81-83, 99,
100
93, 94, 95, 96
Name
A0
A1
A
BWSa
BWSb
BWSc
BWSd
WE
I/O Type
Input-
Synchronous
Input-
Synchronous
Description
CY7C1354V25
CY7C1356V25
Address Inputs used to select one of the 266,144 ad-
dress locations. Sampled at the rising edge of the CLK.
Byte Write Select Inputs, active LOW. Qualified with WE
to conduct writes to the SRAM. Sampled on the rising
edge of CLK. BWSa controls DQa and DPa, BWSb con-
trols DQb and DPb, BWSc controls DQc and DPc, BWSd
controls DQd and DPd.
Write Enable Input, active LOW. Sampled on the rising
edge of CLK if CEN is active LOW. This signal must be
asserted LOW to initiate a write sequence.
Advance/Load Input used to advance the on-chip ad-
dress counter or load a new address. When HIGH (and
CEN is asserted LOW) the internal burst counter is ad-
vanced. When LOW, a new address can be loaded into
the device for an access. After being deselected, ADV/LD
should be driven LOW in order to load a new address.
Clock Input. Used to capture all synchronous inputs to
the device. CLK is qualified with CEN. CLK is only rec-
ognized if CEN is active LOW.
Chip Enable 1 Input, active LOW. Sampled on the rising
edge of CLK. Used in conjunction with CE
2
and CE
3
to
select/deselect the device.
Chip Enable 2 Input, active HIGH. Sampled on the rising
edge of CLK. Used in conjunction with CE
1
and CE
3
to
select/deselect the device.
Chip Enable 3 Input, active LOW. Sampled on the rising
edge of CLK. Used in conjunction with CE
1
and CE
2
to
select/deselect the device.
88
88
Input-
Synchronous
Input-
Synchronous
85
85
ADV/LD
89
89
CLK
Input-Clock
98
98
CE
1
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
97
97
CE
2
92
92
CE
3
86
86
OE
Input-
Output Enable, active LOW. Combined with the synchro-
Asynchronous nous logic block inside the device to control the direction
of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are
three-stated, and act as input data pins. OE is masked
during the data portion of a write sequence , during the
first clock when emerging from a deselected state and
when the device has been deselected.
Input-
Synchronous
Clock Enable Input, active LOW. When asserted LOW
the clock signal is recognized by the SRAM. When deas-
serted HIGH the clock signal is masked. Since deassert-
ing CEN does not deselect the device, CEN can be used
to extend the previous cycle when required.
Bidirectional Data I/O lines. As inputs, they feed into an
on-chip data register that is triggered by the rising edge
of CLK. As outputs, they deliver the data contained in the
memory location specified by A
[17:0]
during the previous
clock rise of the read cycle. The direction of the pins is
controlled by OE and the internal control logic. When OE
is asserted LOW, the pins can behave as outputs. When
HIGH, DQa–DQd are placed in a three-state condition.
The outputs are automatically three-stated during the
data portion of a write sequence, during the first clock
when emerging from a deselected state, and when the
device is deselected, regardless of the state of OE.
87
87
CEN
(a)58, 59, 62, 63,
68, 69, 72–74
(b)8, 9, 12, 13, 18,
19, 22–24
(a)52, 53, 56–59,
62, 63,
(b)68, 69, 72–75,
78, 79
(c)2, 3, 6–9, 12, 13,
(d)18, 19, 22–25,
28, 29
DQa
DQb
DQc
DQd
I/O-
Synchronous
4
PRELIMINARY
Pin Definitions (100-Pin TQFP)
(continued)
x18 Pin Location
74, 24
x36 Pin Location
51, 80, 1, 30
Name
DPa
DPb
DPc
DPd
MODE
I/O Type
I/O-
Synchronous
Description
CY7C1354V25
CY7C1356V25
Bidirectional Data Parity I/O lines. Functionally, these sig-
nals are identical to DQ
[31:0]
. During write sequences,
DPa is controlled by BWSa, DPb is controlled by BWSb,
DPc is controlled by BWSc, and DPd is controlled by
BWSd.
Mode Input. Selects the burst order of the device. Tied
HIGH selects the interleaved burst order. Pulled LOW
selects the linear burst order. MODE should not change
states during operation. When left floating MODE will de-
fault HIGH, to an interleaved burst order.
Power supply inputs to the core of the device.
Power supply for the I/O circuitry.
Ground for the device. Should be connected to ground of
the system.
No connects. Reserved for address expansion to 512K
depths.
Do Not Use pins. These pins should be left floating or tied
to V
SS
.
31
31
Input
Strap Pin
14–16, 41, 65, 66,
91
4, 11, 20, 27, 54,
61, 70, 77
5, 10, 17, 21, 26,
40, 55, 60, 67, 71,
76, 90
NC
38, 39, 42, 43
14–16, 41, 65, 66,
91
4, 11, 20, 27, 54,
61, 70, 77
5, 10, 17, 21, 26,
40, 55, 60, 67, 71,
76, 90
NC
38, 39, 42, 43
V
DD
V
DDQ
V
SS
Power Supply
I/O Power
Supply
Ground
NC
DNU
-
-
5
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