352
CY7C1352
256K x18 Pipelined SRAM with NoBL™ Architecture
Features
• Pin compatible and functionally equivalent to ZBT™
devices MCM63Z818 and MT55L256L18P
• Supports 143-MHz bus operations with zero wait states
— Data is transferred on every clock
• Internally self-timed output buffer control to eliminate
the need to use OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write Capability
• 256K x 18 common I/O architecture
• Single 3.3V power supply
• Fast clock-to-output times
— 4.0 ns (for 143-MHz device)
— 4.2 ns (for 133-MHz device)
— 5.0 ns (for 100-MHz device)
— 7.0 ns (for 80-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Asynchronous output enable
• JEDEC-standard 100-pin TQFP package
• Burst Capability—linear or interleaved burst order
• Low standby power
Functional Description
The CY7C1352 is a 3.3V 256K by 18 synchronous-pipelined
Burst SRAM designed specifically to support unlimited true
back-to-back Read/Write operations without the insertion of
wait states. The CY7C1352 is equipped with the advanced No
Bus Latency™ (NoBL™) logic required to enable consecutive
Read/Write operations with data being transferred on every
clock cycle. This feature dramatically improves the throughput
of the SRAM, especially in systems that require frequent
Read/Write transitions.The CY7C1352 is pin/functionally com-
patible to ZBT™ SRAMs MCM63Z819 and MT55L256L18P.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal, which
when deasserted suspends operation and extends the previ-
ous clock cycle. Maximum access delay from the clock rise is
4.0 ns (143-MHz device).
Write operations are controlled by the four Byte Write Select
(BWS
[1:0]
) and a Write Enable (WE) input. All writes are con-
ducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
18
Logic Block Diagram
CLK
D
Data-In REG.
CE Q
18
18
CONTROL
and WRITE
LOGIC
18
256Kx18
MEMORY
ARRAY
18
ADV/LD
A
[17:0]
CEN
CE
1
CE2
CE3
WE
BWS [1:0]
Mode
CLK
OUTPUT
REGISTERS
and LOGIC
18
DQ
[15:0]
DP
[1:0]
OE
.
Selection Guide
7C1352-143
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Commercial
Commercial
4.0
450
5
7C1352-133
4.2
400
5
7C1352-100
5.0
350
5
7C1352-80
7.0
300
5
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation.
ZBT is a trademark of Integrated Device Technology.
Cypress Semiconductor Corporation
Document #: 38-05080 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised August 20, 2001
CY7C1352
Pin Configuration
100-Pin TQFP
A6
A7
CE
1
CE
2
NC
NC
BWS
1
BWS
0
CE
3
V
DD
V
SS
CLK
WE
CEN
OE
ADV/LD
NC
NC
NC
NC
NC
V
DDQ
V
SS
NC
NC
DQ
8
DQ
9
V
SS
V
DDQ
DQ
10
DQ
11
V
DDQ
V
DD
V
DD
V
SS
DQ
12
DQ
13
V
DDQ
V
SS
DQ
14
DQ
15
DP
1
NC
V
SS
V
DDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
8
A
9
CY7C1352
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
17
NC
NC
V
DDQ
V
SS
NC
DP
0
DQ
7
DQ
6
V
SS
V
DDQ
DQ
5
DQ
4
V
SS
V
DD
V
DD
V
SS
DQ
3
DQ
2
V
DDQ
V
SS
DQ
1
DQ
0
NC
NC
V
SS
V
DDQ
NC
NC
NC
MODE
A
5
A
4
A
3
A
2
A
1
A
0
DNU
DNU
V
SS
V
DD
Document #: 38-05080 Rev. **
DNU
DNU
A
10
A
11
A
12
A
13
A
14
A
15
A
16
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Page 2 of 14
CY7C1352
Pin Definitions
Pin Number
80, 50−44,
81−82, 99−
100, 32−37
94, 93
Name
A
[17:0]
I/O
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Description
Address Inputs used to select one of the 262,144 address locations. Sampled at
the rising edge of the CLK.
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the
SRAM. Sampled on the rising edge of CLK. BWS
0
controls DQ
[7:0]
and DP
0
,
BWS
1
controls DQ
[15:8]
and DP
1
. See Write Cycle Description table for details.
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is
active LOW. This signal must be asserted LOW to initiate a write sequence.
Advance/Load input used to advance the on-chip address counter or load a new
address. When HIGH (and CEN is asserted LOW) the internal burst counter is
advanced. When LOW, a new address can be loaded into the device for an ac-
cess. After being deselected, ADV/LD should be driven LOW in order to load a
new address.
Clock input. Used to capture all synchronous inputs to the device. CLK is qualified
with CEN. CLK is only recognized if CEN is active LOW.
Chip Enable 1 Input active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
2
and CE
3
to select/deselect the device.
Chip Enable 2 Input active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE
1
and CE
3
to select/deselect the device.
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
1
and CE
2
to select/deselect the device.
Output Enable, active LOW. Combined with the synchronous logic block inside
the device to control the direction of the I/O pins. When LOW, the I/O pins are
allowed to behave as outputs. When deasserted HIGH, I/O pins are three-stated,
and act as input data pins. OE is masked during the data portion of a write
sequence, during the first clock when emerging from a deselected state, when
the device has been deselected.
BWS
[1:0]
88
85
WE
ADV/LD
89
98
97
92
86
CLK
CE
1
CE
2
CE
3
OE
Input-Clock
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
Document #: 38-05080 Rev. **
Page 3 of 14
CY7C1352
Pin Definitions
(continued)
Pin Number
87
Name
CEN
I/O
Input-
Synchronous
Description
Clock Enable Input, active LOW. When asserted LOW the clock signal is recog-
nized by the SRAM. When deasserted HIGH the Clock signal is masked. Since
deasserting CEN does not deselect the device, CEN can be used to extend the
previous cycle when required.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that
is triggered by the rising edge of CLK. As outputs, they deliver the data contained
in the memory location specified by A
[16:0]
during the previous clock rise of the
read cycle. The direction of the pins is controlled by OE and the internal control
logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH,
DQ
[15:0]
are placed in a three-state condition. The outputs are automatically
three-stated during the data portion of a write sequence, during the first clock
when emerging from a deselected state, and when the device is deselected,
regardless of the state of OE.
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to
DQ
[15:0]
. During write sequences, DP
0
is controlled by BWS
0
and DP
1
is con-
trolled by BWS
1
Mode input. Selects the burst order of the device. Tied HIGH selects the inter-
leaved burst order. Pulled LOW selects the linear burst order. MODE should not
change states during operation. When left floating, MODE will default HIGH to an
interleaved burst order.
Power supply inputs to the core of the device. Should be connected to 3.3V power
supply.
Power supply for the I/O circuitry. Should be connected to a 3.3V power supply.
23−22, 19−18,
13−12, 9−8,
73−72, 69−68,
63−62, 59−58
DQ
[15:0]
I/O-
Synchronous
24, 74
DP
[1:0]
I/O-
Synchronous
Input
Strap pin
31
MODE
15, 16, 41, 65,
66, 91
4, 11, 14, 20,
27, 54, 61, 70,
77
5, 10, 17, 21,
26, 40, 55, 60,
64, 67, 71, 76,
90
1−3, 6−7, 25,
28−30, 51−53,
56−57, 75,
78−79, 95−96
83, 84
38, 39, 42, 43
V
DD
V
DDQ
Power Supply
I/O Power
Supply
Ground
V
SS
Ground for the device. Should be connected to ground of the system.
NC
-
No Connects. These pins are not connected to the internal device.
NC
DNU
-
-
No Connects. Reserved for address inputs for depth expansion. Pin 83 is re-
served for 512K depth and pin 84 is reserved for 1-Mb depth devices.
Do Not Use pins. These pins should be left floating or tied to V
SS
.
tus of the Write Enable (WE). BWS
[1:0]
can be used to conduct
byte write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been de-
selected in order to load a new address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
1
, CE
2
,
and CE
3
are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs (A
0
−A
17
)
is latched into the Address Register and presented to the
memory core and control logic. The control logic determines
Introduction
Functional Overview
The CY7C1352 is a synchronous-pipelined Burst SRAM de-
signed specifically to eliminate wait states during Write-Read
transitions. All synchronous inputs pass through input regis-
ters controlled by the rising edge of the clock. The clock signal
is qualified with the Clock Enable input signal (CEN). If CEN is
HIGH, the clock signal is not recognized and all internal states
are maintained. All synchronous operations are qualified with
CEN. All data outputs pass through output registers controlled
by the rising edge of the clock. Maximum access delay from
the clock rise (t
CO
) is 4.0 ns (143-MHz device).
Accesses can be initiated by asserting all three chip enables
(CE
1
, CE
2
, CE
3
) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW, the
address presented to the device will be latched. The access
can either be a read or write operation, depending on the sta-
Document #: 38-05080 Rev. **
Page 4 of 14
CY7C1352
that a read access is in progress and allows the requested
data to propagate to the input of the output register. At the
rising edge of the next clock the requested data is allowed to
propagate through the output register and onto the data bus
within 4.0 ns (143-MHz device) provided OE is active LOW.
After the first clock of the read access the output buffers are
controlled by OE and the internal control logic. OE must be
driven LOW in order for the device to drive out the requested
data. During the second clock, a subsequent operation
(Read/Write/Deselect) can be initiated. Deselecting the device
is also pipelined. Therefore, when the SRAM is deselected at
clock rise by one of the chip enable signals, its output will
three-state following the next clock rise.
Burst Read Accesses
The CY7C1352 has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Reads without reasserting the address inputs. ADV/LD
must be driven LOW in order to load a new address into the
SRAM, as described in the Single Read Access section above.
The sequence of the burst counter is determined by the MODE
input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and will
wrap-around when incremented sufficiently. A HIGH input on
ADV/LD will increment the internal burst counter regardless of
the state of chip enables inputs or WE. WE is latched at the
beginning of a burst cycle. Therefore, the type of access (Read
or Write) is maintained throughout the burst sequence.
Single Write Accesses
Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
1
, CE
2
,
and CE
3
are ALL asserted active, and (3) the write signal WE
is asserted LOW. The address presented to A
0
−A
17
is loaded
into the Address Register. The write signals are latched into
the Control Logic block.
On the subsequent clock rise the data lines are automatically
three-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ
[15:0]
and
DP
[1:0]
. In addition, the address for the subsequent access
(Read/Write/Deselect) is latched into the Address Register
(provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQ
[15:0]
and
DP
[1:0]
(or a subset for byte write operations, see Write Cycle
Description table for details) inputs is latched into the device
and the write is complete.
The data written during the Write operation is controlled by
BWS
[1:0]
signals. The CY7C1352 provides byte write capabil-
ity that is described in the write cycle description table. Assert-
ing the Write Enable input (WE) with the selected Byte Write
Select (BWS
[1:0]
) input will selectively write to only the desired
bytes. Bytes not selected during a byte write operation will
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations. Byte write
capability has been included in order to greatly simplify
Read/Modify/Write sequences, which can be reduced to sim-
ple byte write operations.
Because the CY7C1352 is a common I/O device, data should
not be driven into the device while the outputs are active. The
Output Enable (OE) can be deasserted HIGH before present-
ing data to the DQ
[15:0]
and DP
[1:0]
inputs. Doing so will
three-state the output drivers. As a safety precaution, DQ
[15:0]
and DP
[1:0]
are automatically three-stated during the data por-
tion of a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1352 has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Write operations without reasserting the address inputs.
ADV/LD must be driven LOW in order to load the initial ad-
dress, as described in the Single Write Access section above.
When ADV/LD is driven HIGH on the subsequent clock rise,
the chip enables (CE
1
, CE
2
, and CE
3
) and WE inputs are ig-
nored and the burst counter is incremented. The correct
BWS
[1:0]
inputs must be driven in each cycle of the burst write
in order to write the correct bytes of data.
Cycle Description Truth Table
[
1, 2, 3, 4, 5, 6
]
Operation
Deselected
Suspend
Begin Read
Begin Write
Burst READ
Operation
Address
used
External
-
External
External
Internal
CE
1
X
0
0
X
CEN
0
1
0
0
0
ADV/
LD/
L
X
0
0
1
WE
X
X
1
0
X
BWS
x
X
X
X
Valid
X
CLK
L-H
L-H
L-H
L-H
L-H
Comments
I/Os three-state following next rec-
ognized clock.
Clock ignored, all operations
suspended.
Address latched.
Address latched, data presented
two valid clocks later.
Burst Read operation. Previous
access was a Read operation. Ad-
dresses incremented internally in
conjunction with the state of
MODE.
Document #: 38-05080 Rev. **
Page 5 of 14
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