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CY7C1339B
128K x 32 Synchronous Pipelined Cache RAM
Features
• Supports 100-MHz bus for Pentium and PowerPC
operations with zero wait states
• Fully registered inputs and outputs for pipelined
operation
• 128K × 32 common I/O architecture
• 3.3V core power supply
• 2.5V / 3.3V I/O operation
• Fast clock-to-output times
— 3.5 ns (for 166-MHz device)
— 4.0 ns (for 133-MHz device)
•
•
•
•
•
•
— 5.5 ns (for 100-MHz device)
User-selectable burst counter supporting Intel
Pentium interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous output enable
Offered in JEDEC-standard 100-pin TQFP and 119-ball
BGA packages
“ZZ” Sleep Mode and Stop Clock options
The CY7C1339B I/O pins can operate at either the 2.5V or the
3.3V level; the I/O pins are 3.3V-tolerant when V
DDQ
= 2.5V.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise is 3.5 ns (166-MHz
device).
The CY7C1339B supports either the interleaved burst
sequence used by the Intel Pentium processor or a linear burst
sequence used by processors such as the PowerPC. The
burst sequence is selected through the MODE pin. Accesses
can be initiated by asserting either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC) at
clock rise. Address advancement through the burst sequence
is controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte Write operations are qualified with the four Byte Write
Select (BW
[3:0]
) inputs. A Global Write Enable (GW) overrides
all Byte Write inputs and writes data to all four bytes. All Writes
are conducted with on-chip synchronous self-timed Write
circuitry.
Three synchronous Chip Selects (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to provide
proper data during depth expansion, OE is masked during the
first clock of a Read cycle when emerging from a deselected
state.
Functional Description
The CY7C1339B is a 3.3V, 128K by 32 synchronous-pipelined
cache SRAM designed to support zero wait state secondary
cache with minimal glue logic.
Logic Block Diagram
CLK
ADV
ADSC
ADSP
A
[16:0]
GW
BWE
BW
3
BW
2
BW
1
MODE
(A
[1;0]
) 2
BURST Q
0
CE COUNTER
Q
1
CLR
Q
ADDRESS
CE REGISTER
D
D
DQ[31:24] Q
BYTEWRITE
REGISTERS
15
17
17
15
128K × 32
MEMORY
ARRAY
D DQ[23:16] Q
BYTEWRITE
REGISTERS
D
Q
DQ[15:8]
BYTEWRITE
REGISTERS
Q
DQ[7:0]
BYTEWRITE
REGISTERS
D
BW
0
CE
1
CE
2
CE
3
32
32
D
ENABLE Q
CE REGISTER
CLK
D
Q
ENABLE DELAY
REGISTER
CLK
OUTPUT
REGISTERS
CLK
INPUT
REGISTERS
CLK
OE
ZZ
SLEEP
CONTROL
DQ
[31:0]
Cypress Semiconductor Corporation
Document #: 38-05141 Rev. *A
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised March 27, 2002
CY7C1339B
Selection Guide
7C1339B-166
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
3.5
420
10
7C1339B-133
4.0
375
10
7C1339B-100
5.5
325
10
Unit
ns
mA
mA
Pin Configurations
A6
A7
CE
1
CE
2
BW
3
BW
2
BW
1
BW
0
CE
3
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
8
A
9
NC
DQ
16
DQ
17
V
DDQ
V
SSQ
DQ
18
DQ
19
DQ
20
DQ
21
V
SSQ
V
DDQ
DQ
22
DQ
23
NC
V
DD
NC
V
SS
DQ
24
DQ
25
V
DDQ
V
SSQ
DQ
26
DQ
27
DQ
28
DQ
29
V
SSQ
V
DDQ
DQ
30
DQ
31
NC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
BYTE2
BYTE3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100-pin TQFP
CY7C1339B
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
DQ
15
DQ
14
V
DDQ
V
SSQ
DQ
13
DQ
12
DQ
11
DQ
10
V
SSQ
V
DDQ
DQ
9
DQ
8
V
SS
NC
V
DD
ZZ
DQ
7
DQ
6
V
DDQ
V
SSQ
DQ
5
DQ
4
DQ
3
DQ
2
V
SSQ
V
DDQ
DQ
1
DQ
0
NC
BYTE1
BYTE0
Document #: 38-05141 Rev. *A
MODE
A
5
A
4
A
3
A
2
A
1
A
0
DNU
DNU
V
SS
V
DD
DNU
DNU
A
10
A
11
A
12
A
13
A
14
A
15
A
16
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Page 2 of 17
CY7C1339B
Pin Configurations
(continued)
119-ball BGA
CY7C1339B (128K × 32)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQ
c
DQ
c
V
DDQ
DQ
c
DQ
c
V
DDQ
DQ
d
DQ
d
V
DDQ
DQ
d
DQ
d
NC
NC
V
DDQ
2
A
CE
2
A
NC
DQ
c
DQ
c
DQ
c
DQ
c
V
DD
DQ
d
DQ
d
DQ
d
DQ
d
NC
A
NC
DNU
3
A
A
A
V
SS
V
SS
V
SS
BW
c
V
SS
NC
V
SS
BW
d
V
SS
V
SS
V
SS
MODE
A
DNU
4
ADSP
ADSC
V
DD
NC
CE
1
OE
ADV
GW
V
DD
CLK
NC
BWE
A1
A0
V
DD
A
DNU
5
A
A
A
V
SS
V
SS
V
SS
BW
b
V
SS
NC
V
SS
BW
a
V
SS
V
SS
V
SS
V
DD
A
DNU
6
A
NC
A
NC
DQ
b
DQ
b
DQ
b
DQ
b
V
DD
DQ
a
DQ
a
DQ
a
DQ
a
NC
A
NC
NC
7
V
DDQ
NC
NC
DQ
b
DQ
b
V
DDQ
DQ
b
DQ
b
V
DDQ
DQ
a
DQ
a
V
DDQ
DQ
a
DQ
a
NC
ZZ
V
DDQ
Document #: 38-05141 Rev. *A
Page 3 of 17
CY7C1339B
Pin Definitions
Pin Name
A
[16:0]
I/O
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-Clock
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Pin Description
Address Inputs used to select one of the 64K address locations. Sampled at the rising edge of the
CLK if ADSP or ADSC is active LOW, and CE
1
, CE
2
, and CE
3
are sampled active. A
[1:0]
feed the
two-bit counter.
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global
Write is conducted (ALL bytes are written, regardless of the values on BW
[3:0]
and BWE).
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a Byte Write.
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
2
and CE
3
to select/deselect the device. ADSP is ignored if CE
1
is HIGH.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE
1
and CE
3
to select/deselect the device.
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
1
and CE
2
to select/deselect the device.
BW
[3:0]
GW
BWE
CLK
CE
1
CE
2
CE
3
OE
Input-
Output Enable, Asynchronous Input, active LOW. Controls the direction of the I/O pins. When LOW,
Asynchronous the I/O pins behave as outputs. When deserted HIGH, I/O pins are three-stated, and act as input
data pins. OE is masked during the first clock of a Read cycle when emerging from a deselected
state.
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Advance Input Signal, sampled on the rising edge of CLK. When asserted, it automatically incre-
ments the address in a burst cycle.
Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW, A
[16:0]
is captured in the address registers. A
[1:0]
are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE
1
is deserted HIGH.
Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW, A
[16:0]
is captured in the address registers. A
[1:0]
are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized.
ADV
ADSP
ADSC
ZZ
Input-
ZZ “sleep” Input. This active HIGH input places the device in a non-time-critical “sleep” condition
Asynchronous with data integrity preserved. Leaving ZZ floating or NC will default the device into an active state.
ZZ has an internal pull down.
I/O-
Synchronous
Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by
the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by A
[16:0]
during the previous clock rise of the Read cycle. The direction of the pins is controlled
by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQ
[31:0]
are placed
in a three-state condition.
Ground for the core of the device. Should be connected to ground of the system.
Power supply for the I/O circuitry. Should be connected to a 3.3V or 2.5V power supply.
Ground for the I/O circuitry. Should be connected to ground of the system.
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V
DDQ
or left
floating selects interleaved burst sequence. This is a strap pin and should remain static during
device operation. When left floating or NC, defaults to interleaved burst order. Mode pin has an
internal pull up.
No Connects.
Do Not Use pins. These pins could be left floating or tied to GND.
DQ
[31:0]
V
DD
V
SS
V
DDQ
V
SSQ
MODE
Power Supply Power supply inputs to the core of the device. Should be connected to 3.3V power supply.
Ground
I/O Power
Supply
I/O Ground
Input-
Static
NC
DNU
–
-
Document #: 38-05141 Rev. *A
Page 4 of 17
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