ADVANCED INFORMATION
CY7C1331
CY7C1332
64K x 18 Synchronous
Cache 3.3V RAM
Features
• Supports 66-MHz Pentium™ processor cache systems
with zero wait states
•
Single 3.3V power supply
•
64K by 18 common I/O
•
Fast clock-to-output times
— 8.5 ns
•
Two-bit wraparound counter supporting the Pentium
and 486 burst sequence (7C1331)
•
Two-bit wraparound counter supporting linear burst se-
quence (7C1332)
•
Separate processor and controller address strobes
•
Synchronous self-timed write
•
Direct interface with the processor and external cache
controller
•
Asynchronous output enable
•
JEDEC-standard pinout
•
52-pin PLCC and PQFP packaging
Functional Description
The CY7C1331 and CY7C1332 are 3.3V 64K by 18 synchro-
nous cache RAMs designed to interface with high-speed mi-
croprocessors with minimum glue logic. Maximum access de-
lay from clock rise is 8.5 ns. A 2-bit on-chip counter captures
the first address in a burst and increments the address auto-
matically for the rest of the burst access.
The CY7C1331 is designed for Intel Pentium and i486
CPU-based systems; its counter follows the burst sequence of
the Pentium and the i486 processors. The CY7C1332 is archi-
tected for processors with linear burst sequences. Burst ac-
cesses can be initiated with the processor address strobe (AD-
SP) or the cache controller address strobe (ADSC) inputs.
Address advancement is controlled by the address advance-
ment (ADV) input.
A synchronous self-timed write mechanism is provided to sim-
plify the write interface. A synchronous chip select input and
an asynchronous output enable input provide easy control for
bank selection and output three-state control.
LogicBlockDiagram
18
DATA
IN
REGISTER
ADDR
REG
9
14
16
2
ADV
ADV
LOGIC
2
64K X 9
64K X 9
RAM ARRAY RAM ARRAY
9
DQ
8
DQ
9
V
CCQ
V
SSQ
DQ
10
DQ
11
DQ
12
DQ
13
V
SSQ
V
CCQ
DQ
14
DQ
15
[2]
DP1
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin Configuration
PLCC
Top View
WH
WL
ADSC
ADSP
ADV
CLK
A6
A7
CS
A
8
A
9
A10
OE
16
A
15
– A
0
14
CLK
ADSP
ADSC
CS
WH
WL
TIMING
CONTROL
WH
WL
9
9
7 6 5 4 3 2 1 52 51 50 49 48 47
46
45
44
43
42
41
7C1331
7C1332
40
39
38
37
36
35
34
2122 23 24 25 26 27 28 29 30 31 32 33
A1
A0
GND
V CC
A
15
A14
A13
A12
A11
A5
A4
A3
A2
DP
0
DQ
7
DQ
6
V
CCQ
V
SSQ
DQ
5
DQ
4
DQ
3
DQ
2
V
SSQ
V
CCQ
DQ
1
DQ
0
[2]
18
DQ
15
– DQ
0
DP
1
– DP
0
OE
1331– 2
1331–1
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Notes:
1. DP
0
and DP
1
are functionally equivalent to DQ
x
.
Pentium is a trademark of Intel Corporation.
Commercial
Military
7C1331–8
7C1332–8
8.5
200
7C1331–10
7C1332–10
10
200
7C1331–12
7C1332–12
12
170
200
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134 •
408-943-2600
December 1992 - Revised April 1995
ADVANCED INFORMATION
Functional Description
(continued)
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are sat-
isfied at clock rise: (1) CS is LOW and (2) ADSP is LOW. AD-
SP-triggered write cycles are completed in two clock periods.
The address at A
0
through A
15
is loaded into the address reg-
ister and address advancement logic and delivered to the RAM
core. The write signal is ignored in this cycle because the
cache tag or other external logic uses this clock period to per-
form address comparisons or protection checks. If the write is
allowed to proceed, the write input to the CY7C1331 and
CY7C1332 will be pulled LOW before the next clock rise.
ADSP is ignored if CS is HIGH.
If WH, WL, or both are LOW at the next clock rise, information pre-
sented at DQ
0
- DQ
15
and DP
0
- DP
1
will be written into the location
specified by the address advancement logic. WL controls the writing
of DQ
0
- DQ
7
and DP0 while WH controls the writing of DQ
8
- DQ
15
and DP
1
. Because the CY7C1331 and CY7C1332 are common-I/O
devices, the output enable signal (OE) must be deasserted before
data from the CPU is delivered to DQ
0
- DQ
15
and DP
0
- DP
1
. As a
safety precaution, the appropriate data lines are three-stated in the
cycle where WH, WL, or both are sampled LOW, regardless of the
state of the OE input.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at rising edge of the clock: (1) CS is LOW, (2) ADSC is
LOW, and (3) WH or WL are LOW. ADSC triggered accesses are
completed in a single clock cycle.
The address at A
0
through A
15
is loaded into the address register
and address advancement logic and delivered to the RAM core.
Information presented at DQ
0
- DQ
15
and DP
0
- DP
1
will be written
into the location specified by the address advancement logic. WL
controls the writing of DQ
0
- DQ
7
and DP
0
while WH controls the
writing of DQ
8
- DQ
15
and DP
1
. Since the CY7C1331 and the
CY7C1332 are common-I/O devices, the output enable signal (OE)
must be deasserted before data from the cache controller is deliv-
ered to the data lines. As a safety precaution, the appropriate
data lines are three-stated in the cycle where WH, WL, or both
are sampled LOW, regardless of the state of the OE input.
CY7C1331
CY7C1332
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CS is LOW, (2) ADSP or ADSC
is LOW, and (3) WH and WL are HIGH. The address at A0
through A15 is stored into the address advancement logic and
delivered to the RAM core. If the output enable (OE) signal is
asserted (LOW), data will be available at the data outputs a
maximum of 8.5 ns after clock rise.
Burst Sequences
The CY7C1331 provides a 2-bit wraparound counter, fed by
pins A
0
- A
1
, that implements the Intel 80486 and Pentium pro-
cessor address burst sequence (see
Table 1).
Note that the
burst sequence depends on the first burst address.
Table 1. Counter Implementation for the Intel
Pentium/80486 Processor’s Sequence
First
Second
Third
Fourth
Address
Address
Address
Address
A
X + 1
, A
x
A
X + 1
, A
x
A
X + 1
, A
x
A
X + 1
, A
x
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
The CY7C1332 provides a two-bit wraparound counter, fed by
pins A0 - A1, that implements a linear address burst sequence (see
Table 2).
Table 2. Counter Implementation for a Linear Sequence
First
Second
Third
Fourth
Address
Address
Address
Address
A
X + 1
, A
x
A
X + 1
, A
x
A
X + 1
, A
x
A
X + 1
, A
x
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Application Example
Figure 1
shows a 512-Kbyte secondary cache for a hypothet-
ical 3.3V, 66-MHz Pentium or i486 processor using four
CY7C1331 cache RAMs.
512 KB
66–MHz OSC
CLK
ADR
DATA
PENTIMUM
OR
i486
PROCESSOR
ADS
CLK
ADR
DATA
ADSP
ADSC
ADV
OE
WH, WL
WH, WL
2
2
2
WH
2
,
WL
2
2
WH
3
,
WL
3
INTERFACE TO
MAIN MEMORY
WH, WL
WH, WL
7C1331
CLK
ADR
CACHE TAG
DATA
MATCH
DIRTY
VALID
WH
1
,
CLK ADSC ADV OE WH
0
,
WL
1
WL
0
ADR
DATA
ADSP
CACHE
CONTROLLER
MATCH
DIRTY
VALID
1331– 3
Figure 1. Cache Using Four CY7C1331s.
2
ADVANCED INFORMATION
Pin Definitions
Signal Name
V
CC
V
CCQ
GND
V
SSQ
CLK
A
15
– A
0
ADSP
ADSC
WH
WL
ADV
OE
CS
DQ
15
–DQ
0
DP
1
–DP
0
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input/Output
Input/Output
Type
# of Pins
1
4
1
4
1
16
1
1
1
1
1
1
1
16
2
+3.3V
Power
+3.3V
(Outputs)
Ground
Ground (Outputs)
Clock
Address
Address Strobe from Processor
Address Strobe from Cache Controller
Write Enable – High Byte
Write Enable – Low Byte
Advance
Output Enable
Chip Select
Regular Data
Parity Data
Description
CY7C1331
CY7C1332
Pin Descriptions
Signal
Name
CLK
I/O
I
Description
Clock signal. It is used to capture the ad-
dress, the data to be written, and the fol-
lowing control signals: ADSP ADSC, WH,
,
WL, CS, and ADV. It is also used to ad-
vance the on-chip auto-address-increment
logic (when the appropriate control signals
have been set).
Sixteen address lines used to select one of
64K locations. They are captured in an
on-chip register on the rising edge of CLK
if ADSP or ADSC is LOW. The rising edge
of the clock also loads the lower two ad-
dress lines, A
1
- A
0
, into the on-chip au-
to-address-increment logic if ADSP or
ADSC is LOW.
Address strobe from processor. This signal
is sampled at the rising edge of CLK. When
this input and/or ADSC is asserted, A
0
-A
15
will be captured in the on-chip address reg-
ister. It also allows the lower two address
bits to be loaded into the on-chip auto-ad-
dress-increment logic. If both ADSP and
ADSC are asserted at the rising edge of
CLK, only ADSP will be recognized. The
ADSP input should be connected to the
ADS output of the processor. ADSP is ig-
nored when CS is HIGH.
Pin Descriptions
(continued)
Signal
Name
ADSC
I/O
I
Description
Address strobe from cache controller. This
signal is sampled at the rising edge of CLK.
When this input and/or ADSP is asserted,
A
0
-A
15
will be captured in the on-chip ad-
dress register. It also allows the lower two
address bits to be loaded into the on-chip
auto-address-increment logic. The ADSC
input should
not
be connected to the ADS
output of the processor.
Write signal for the high-order half of the
RAM array. This signal is sampled by the
rising edge of CLK. If WH is sampled as
LOW, i.e., asserted, the control logic will
perform a self-timed write of DQ
15
- DQ
8
and DP
1
from the on-chip data register into
the selected RAM location. There is one
exception to this. If ADSP, WH, and CS are
asserted (LOW) at the rising edge of CLK,
the write signal, WH, is ignored. Note that
ADSP has no effect onWH if CS is HIGH.
Write signal for the low-order half of the
RAM array. This signal is sampled by the
rising edge of CLK. If WL is sampled as
LOW, i.e., asserted, the control logic will
perform a self-timed write of DQ
7
- DQ
0
and DP
0
from the on-chip data register into
the selected RAM location. There is one
exception to this. If ADSP ,WL, and CS are
asserted (LOW) at the rising edge of CLK,
the write signal, WL, is ignored. Note that
ADSP has no effect on WL if CS is HIGH.
A
15
-A
0
I
WH
I
ADSP
I
WL
I
3
ADVANCED INFORMATION
Pin Descriptions
(continued)
Signal
Name
ADV
CY7C1331
CY7C1332
Pin Descriptions
(continued)
Signal
Name
I/O
Description
I/O
I
Description
Advance. This signal is sampled by the ris-
ing edge of CLK. When it is asserted, it
automatically increments the two-bit
on-chip auto-address-increment counter.
In the CY7C1332, the address will be in-
cremented linearly. In the CY7C1331, the
address will be incremented according to
the Pentium/486 burst sequence. This sig-
nal is ignored if ADSP or ADSC is asserted
concurrently with CS. Note that ADSP has
no effect on ADV if CS is HIGH.
Chip select. This signal is sampled by the
rising edge of CLK. If CS is HIGH and
ADSC is LOW, the SRAM is deselected. If
CS is LOW and ADSC or ADSP is LOW, a
new address is captured by the address
register. If CS is HIGH, ADSP is ignored.
Output enable. This signal is an asynchro-
nous input that controls the direction of the
data I/O pins. If OE is asserted (LOW), the
data pins are outputs, and the SRAM can
be read (as long as CS was asserted when
it was sampled at the beginning of the cy-
cle). If OE is deasserted (HIGH), the data
I/O pins will be three-stated, functioning as
inputs, and the SRAM can be written.
Bidirectional Signals
DQ
15
-DQ
0
I/O
Sixteen bidirectional data I/O lines. DQ
15
-
DQ
8
are inputs to and outputs from the
high-order half of the RAM array, while DQ
7
- DQ
0
are inputs to and outputs from the
low-order half of the RAM array. As inputs,
they feed into an on-chip data register that
is triggered by the rising edge of CLK. As
outputs, they carry the data read from the
selected location in the RAM array. The di-
rection of the data pins is controlled by OE:
when OE is high, the data pins are
three-stated and can be used as inputs;
when OE is low, the data pins are driven by
the output buffers and are outputs. DQ
15
-
DQ
8
and DQ
7
- DQ
0
are also three-stated
when WH and WL, respectively, are sam-
pled LOW at clock rise.
Two bidirectional data I/O lines. These op-
erate in exactly the same manner as DQ
15
- DQ
0
, but are named differently because
their primary purpose is to store parity bits,
while the DQs’ primary purpose is to store
ordinary data bits. DP
1
is an input to and
an output from the high-order half of the
RAM array, while DP
0
is an input to and an
output from the lower-order half of the RAM
array.
CS
I
OE
I
DP
1
-DP
0
I/O
4
ADVANCED INFORMATION
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ...................................–65
°
C to +150
°
C
Ambient Temperature with
Power Applied ...............................................–55
°
C to +125
°
C
Supply Voltage on V
CC
Relative to GND................ –0.5V to +3.6V
DC Voltage Applied to Outputs
in High Z State
[2]
...............................................–0.5V to V
CC
+ 0.3V
DC Input Voltage
[2]
...........................................–0.5V to V
CC
+ 0.3V
Current into Outputs (LOW) ......................................... 20 mA
CY7C1331
CY7C1332
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
Operating Range
Range
Com’l
Mil
Ambient
Temperature
[3]
0
°
C to + 70
°
C
–55
°
C to + 125
°
C
V
CC
, V
CCQ
3.3V
±
0.3V
3.3V
±
0.3V
Electrical Characteristics
Over the Operating Range
[4]
7C1331–8
7C1332–8
Parameter
V
OH
V
OL
V
IH
V
IL
I
X
I
OZ
I
OS
I
CC
I
SB1
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[2]
Input Load Current
Output Leakage
Current
Output Short Circuit
Current
[5]
V
CC
Operating Supply
Current
GND
≤
V
I
≤
V
CC
GND
≤
V
I
≤
V
CC
,
Output Disabled
V
CC
= Max., V
OUT
= GND
V
CC
=Max.,Iout=0mA, Com’l
f=f
MAX
=1/t
CYC
Mil
Test Conditions
V
CC
= Min., I
OH
=–2.0 mA
V
CC
= Min., I
OL
=2.0 mA
2.0
–0.3
–1
–5
Min.
2.4
0.4
V
CC
+0.3V
0.8
+1
+5
–300
200
60
2.0
–0.3
–1
–5
Max.
7C1331–10
7C1332–10
Min.
2.4
0.4
V
CC
+0.3V
0.8
+1
+5
–300
200
60
2.0
–0.3
–1
–5
Max.
7C1331–12
7C1332–12
Min.
2.4
0.4
V
CC
+0.3V
0.8
+1
+5
–300
170
200
40
40
20
20
20
20
mA
mA
Min.
Unit
V
V
V
V
µA
µA
mA
mA
Automatic CE
Max. V
CC
, CS
≥
V
IH
, Com’l
Power-Down Current – V
IN
≥
V
IH
or V
IN
≤
V
IL
,
Mil
TTL Inputs
f=f
MAX
Automatic CE
Power-Down Current
–CMOS Inputs
Max. V
CC
, CS
≥
V
CC
Com’l
–0.3V, V
IN
≥
V
CC
Mil
–0.3V or V
IN
≤
0.3V,
f=f
MAX[6]
I
SB2
Notes:
2. Minimum voltage equals – 2.0V for pulse durations of less than 20 ns.
3. T
A
is the “instant on” case temperature.
4. See the last page of this specification for Group A subgroup testing information.
5. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
Capacitance
[7]
Parameter
C
IN
: Addresses
C
IN
: Other Inputs
C
OUT
Description
Input Capacitance
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25
°
C, f = 1 MHz,
V
CC
= 3.3V
Com’l
Mil
Com’l
Mil
Com’l
Mil
Max.
5
6
5
8
8
16
pF
pF
Unit
pF
5
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