PRELIMINARY
CY7C1316V18
CY7C1318V18
CY7C1320V18
18-Mb DDR-II SRAM Two-word
Burst Architecture
Features
• 18-Mb density (2M x 8, 1M x 18, 512K x 36)
— Supports concurrent transactions
• 250-MHz clock for high vandwidth
• Two-word burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces (data transferred at
500 MHz) @ 250 MHz
• Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
• Two output clocks (C and C) accounts for clock skew
and flight time mismatches
• Echo clocks (CQ and CQ) simplify data capture in high
speed systems
• Synchronous internally self-timed writes
• 1.8V core power supply with HSTL inputs and outputs
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V–V
DD
)
• 13x15 mm 1.0-mm pitch fBGA package, 165 ball (11x15
matrix)
• JTAG interface
• On-chip Delay Lock Loop (DLL)
Functional Description
The CY7C1316V18/CY7C1318V18/CY7C1320V18 are 1.8V
Synchronous Pipelined SRAM equipped with DDR-II (Double
Data Rate) architecture. The DDR-II consists of an SRAM core
with advanced synchronous peripheral circuitry and a 1-bit
burst counter. Addresses for Read and Write are latched on
alternate rising edges of the input (K) clock.Write data is regis-
tered on the rising edges of both K and K. Read data is driven
on the rising edges of C and C if provided, or on the rising edge
of K and K if C/C are not provided. Each address location is
associated with two 8-bit words in the case of CY7C1316V18
that burst sequentially into or out of the device. The burst
counter always starts with a “0” internally in the case of
CY7C1316V18. On CY7C1318V18 and CY7C1320V18, the
burst counter takes in the least significant bit of the external
address and bursts two 18-bit words in the case of
CY7C1318V18 and two 36-bit words in the case of
CY7C1320V18 sequentially into or out of the device.
Asynchronous inputs include impedance match (ZQ).
Synchronous data outputs (Q, sharing the same physical pins
as the data inputs D) are tightly matched to the two output echo
clocks CQ/CQ, eliminating the need for separately capturing
data from each individual DDR SRAM in the system design.
Output data clocks (C/C) enable maximum system clocking
and data synchronization flexibility.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Configurations
CY7C1316V18 – 2M x 8
CY7C1318V18 – 1M x 18
CY7C1320V18 – 512K x 36
Logic Block Diagram (CY7C1316V18)
Burst
Logic
A
(19:0)
20
LD
K
K
Write Add. Decode
Read Add. Decode
Address
Register
Write
Reg
1M x 8 Array
Write
Reg
1M x 8 Array
8
Output
Logic
Control
CLK
Gen.
R/W
C
C
CQ
Read Data Reg.
16
Control
Logic
8
Reg.
8
Reg.
8
Reg.
V
REF
R/W
BWS
[1:0]
8
CQ
DQ
[7:0]
Cypress Semiconductor Corporation
Document #: 38-05177 Rev. *A
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised July 31, 2002
PRELIMINARY
Logic Block Diagram (CY7C1318V18)
A
(0)
20
A
(19:0)
19
CY7C1316V18
CY7C1318V18
CY7C1320V18
Burst
Logic
Write Add. Decode
Read Add. Decode
Address
A
(19:1)
Register
LD
Write
Reg
512K x 18 Array
Write
Reg
512K x 18 Array
18
Output
Logic
Control
K
K
CLK
Gen.
R/W
C
C
CQ
Read Data Reg.
36
Control
Logic
18
Reg.
18
Reg.
18
Reg.
V
REF
R/W
BWS
[1:0]
CQ
18
DQ
[17:0]
Logic Block Diagram (CY7C1320V18)
A
(0)
19
A
(18:0)
18
Burst
Logic
Write Add. Decode
Read Add. Decode
Address
A
(18:1)
Register
LD
Write
Reg
256K x 36 Array
Write
Reg
256K x 36 Array
36
K
K
CLK
Gen.
Output
Logic
Control
R/W
C
C
CQ
36
Read Data Reg.
144
Control
Logic
72
Reg.
72
Reg.
36
Reg.
V
REF
R/W
BWS
[3:0]
CQ
36
DQ
[35:0]
Selection Guide
[1]
300 MHz
Maximum Operating Frequency
Maximum Operating Current
Note:
1. Shaded cells indicate advanced information.
250 MHz
250
TBD
200 MHz
200
TBD
167 MHz
167
TBD
Unit
MHz
mA
300
TBD
Document #: 38-05177 Rev. *A
Page 2 of 24
PRELIMINARY
Pin Configurations
CY7C1316V18 (2M x 8) - 11 x 15 FBGA
CY7C1316V18
CY7C1318V18
CY7C1320V18
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
V
SS
/72M
NC
NC
NC
NC
NC
NC
V
REF
NC
NC
DQ6
NC
NC
NC
TCK
3
A
NC
NC
NC
DQ4
NC
DQ5
V
DDQ
NC
NC
NC
NC
NC
DQ7
A
4
R/W
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
BWS
1
NC
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
NC
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
LD
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
V
SS
/36M
NC
NC
NC
NC
NC
NC
V
REF
DQ1
NC
NC
NC
NC
NC
TMS
11
CQ
DQ3
NC
NC
DQ2
NC
NC
ZQ
NC
NC
DQ0
NC
NC
NC
TDI
CY7C1318V18 (1M x 18) - 11 x 15 FBGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
V
SS
/72M
DQ9
NC
NC
NC
DQ12
NC
V
REF
NC
NC
DQ15
NC
NC
NC
TCK
3
A
NC
NC
DQ10
DQ11
NC
DQ13
V
DDQ
NC
DQ14
NC
NC
DQ16
DQ17
A
4
R/W
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
BWS
1
NC
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
A0
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
NC
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
LD
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
V
SS
/36M
NC
DQ7
NC
NC
NC
NC
V
REF
DQ4
NC
NC
DQ1
NC
NC
TMS
11
CQ
DQ8
NC
NC
DQ6
DQ5
NC
ZQ
NC
DQ3
DQ2
NC
NC
DQ0
TDI
Document #: 38-05177 Rev. *A
Page 3 of 24
PRELIMINARY
Pin Configurations
(continued)
CY7C1320V18 (512K x 36) - 11 x 15 FBGA
CY7C1316V18
CY7C1318V18
CY7C1320V18
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
DQ27
NC
DQ29
NC
DQ30
DQ31
V
REF
NC
NC
DQ33
NC
DQ35
NC
TCK
3
DQ18
DQ28
DQ19
DQ20
DQ21
DQ22
V
DDQ
DQ32
DQ23
DQ24
DQ34
DQ25
DQ26
A
4
R/W
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
BWS
2
BWS
3
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
A0
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
BWS
1
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
LD
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
V
SS
/72M
NC
DQ17
NC
DQ15
NC
NC
V
REF
DQ13
DQ12
NC
DQ11
NC
DQ9
TMS
11
CQ
DQ8
DQ7
DQ16
DQ6
DQ5
DQ14
ZQ
DQ4
DQ3
DQ2
DQ1
DQ10
DQ0
TDI
V
SS
/144M NC/36M
Pin Definitions
Pin Name
DQ
[x:0]
I/O
Pin Description
Input/Output-
Data input/Output signals.
Inputs are sampled on the rising edge of K and K clocks during valid
Synchronous write operations. These pins drive out the requested data during a Read operation. Valid data is
driven out on the rising edge of both the C and C clocks during Read operations or K and K when
in single clock mode. When the Read port is deselected, Q
[x:0]
are automatically three-stated.
CY7C1316V18
−
DQ
[7:0]
CY7C1318V18
−
DQ
[17:0]
CY7C1320V18− DQ
[35:0]
Input-
Synchronous load.
This input is brought LOW when a bus cycle sequence is to be defined. This
Synchronous definition includes address and read/write direction. All transactions operate on a burst of 2 data.
LD
BWS
0
, BWS
1
,
Input-
Byte Write Select 0, 1, 2, and 3
−
active LOW.
Sampled on the rising edge of the K and K clocks
BWS
2
, BWS
3
Synchronous during write operations. Used to select which byte is written into the device during the current
portion of the write operations. Bytes not written remain unaltered.
CY7C1311V18
−
BWS
0
controls D
[3:0]
and BWS
1
controls D
[7:4]
.
CY7C1313V18
−
BWS
0
controls D
[8:0]
and BWS
1
controls D
[17:9].
CY7C1315V18
−
BWS
0
controls D
[8:0]
, BWS
1
controls D
[17:9]
, BWS
2
controls D
[26:18]
and BWS
3
controls D
[35:27]
.
All the byte writes are sampled on the same edge as the data. Deselecting a Byte Write Select
will cause the corresponding byte of data to be ignored and not written into the device.
A, A0
Input-
Address inputs.
These address inputs are multiplexed for both Read and Write operations.
Synchronous Internally, the device is organized as 2M x 8 (2 arrays each of 1M x 8) for CY7C1316V18, 1M x
18 (2 arrays each of 512K x 18) for CY7C1318V18 and 512K x 36 (2 arrays each of 256K x 36)
for CY7C1320V18.
CY7C1316V18 – Since the least significant bit of the address internally is a “0,” only 20 external
address inputs are needed to access the entire memory array.
CY7C1318V18 – A0 is the input to the burst counter. These are incremented in a linear fashion
internally. 20 address inputs are needed to access the entire memory array.
CY7C1320V18 – A0 is the input to the burst counter. These are incremented in a linear fashion
internally. 19 address inputs are needed to access the entire memory array. All the dress inputs
are ignored when the appropriate port is deselected.
Document #: 38-05177 Rev. *A
Page 4 of 24
PRELIMINARY
Pin Definitions
(continued)
Pin Name
R/W
I/O
Pin Description
CY7C1316V18
CY7C1318V18
CY7C1320V18
Input-
Synchronous Read/Write Input.
When LD is LOW, this input designates the access type (READ
Synchronous when R/W is HIGH, WRITE when R/W is low) for loaded address. R/W must meet the set-up and
hold times around edge of K.
Input-
Clock
Input-
Clock
Input-
Clock
Input-
Clock
Positive Output Clock Input.
C is used in conjunction with C to clock out the Read data from
the device. C and C can be used together to deskew the flight times of various devices on the
board back to the controller. See application example for further details.
Negative Output Clock Input.
C is used in conjunction with C to clock out the Read data from
the device. C and C can be used together to deskew the flight times of various devices on the
board back to the controller. See application example for further details.
Positive Input Clock Input.
The rising edge of K is used to capture synchronous inputs to the
device and to drive out data through Q
[x:0]
when in single clock mode. All accesses are initiated
on the rising edge of K.
Negative Input Clock Input.
K is used to capture synchronous data being presented to the device
and to drive out data through Q
[x:0]
when in single clock mode.
C
C
K
K
CQ
Echo Clock
CQ is referenced with respect to C.
This is a free running clock and is synchronized to the
output clock of the QDR
TM
-II. In the single clock mode, CQ is generated with respect to K. The
timings for the echo clocks are shown in the AC timing table.
Echo Clock
CQ is referenced with respect to C.
This is a free running clock and is synchronized to the
output clock of the QDR
TM
-II. In the single clock mode, CQ is generated with respect to K. The
timings for the echo clocks are shown in the AC timing table.
Input
Output Impedance Matching Input.
This input is used to tune the device outputs to the system
data bus impedance. Q
[x:0]
output impedance are set to 0.2 x RQ, where RQ is a resistor
connected between ZQ and ground. Alternately, this pin can be connected directly to V
DD
, which
enables the minimum impedance mode. This pin cannot be connected directly to GND or left
unconnected.
DLL Turn Off.
Connecting this pin to ground will turn off the DLL inside the device. The timings
in the DLL turned off operation will be different from those listed in this data sheet. More details
on this operation can be found in the application note, “DLL Operation in the QDR
TM
-II.”
TDO for JTAG.
TCK pin for JTAG.
TDI pin for JTAG.
TMS pin for JTAG.
No connects.
Can be tied to any voltage level.
Address expansion for 36M.
This is not connected to the die.
Address expansion for 72M.
This is not connected to the die and so can be tied to any voltage
level.
Address expansion for 72M.
This must be tied LOW on the 18M SRAM.
Address expansion for 144M.
This must be tied LOW on the 18M SRAM.
Address expansion for 288M.
This must be tied LOW on the 18M SRAM.
Reference Voltage Input.
Static input used to set the reference level for HSTL inputs and Outputs
as well as A/C measurement points.
Ground for the device.
Should be connected to ground of the system.
CQ
ZQ
DOFF
Input
TDO
TCK
TDI
TMS
NC
NC/36M
NC/72M
V
SS
/72M
V
SS
/144M
V
SS
/288M
V
REF
V
DD
V
SS
V
DDQ
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input-
Reference
Ground
Power Supply
Power supply inputs to the core of the device.
Should be connected to 1.8V power supply.
Power Supply
Power supply inputs for the outputs of the device.
Should be connected to 1.5V power supply.
Document #: 38-05177 Rev. *A
Page 5 of 24
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