CY7C1301A
256K X 36 Dual I/O, Dual Address Synchronous SRAM
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Fast Clock Speed: 100 and 83 MHz
Fast Access Times: 5.0/6.0 ns Max.
Single Clock Operation
Single 3.3V –5% and +5% power supply VCC
Separate V
CCQ
for output buffer
Two Chip Enables for simple depth expansion
Address, Data Input, CE1X, CE2X, CE1Y, CE2Y, PTX,
PTY, WEX, WEY, and Data Output Registers On-Chip
Concurrent Reads and Writes
Two bidirectional Data Buses
Can be configured as separate I/O
Pass-Through feature
Asynchronous Output Enables (OEX, OEY)
LVTTL-Compatible I/O
Self-Timed write
Automatic power-down
176-Pin TQFP Package
The CY7C1301A allows the user to concurrently perform
reads, writes, or pass-through cycles in combination on the
two data ports. The two address ports (AX, AY) determine the
read or write locations for their respective data ports (DQX,
DQY).
All input pins except Output Enable pins (OEX, OEY) are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, depth-expansion Chip Enables
(CE1X, CE2X, CE1Y and CE2Y), Pass-Through controls (PTX
and PTY), and Read-Write control (WEX and WEY).
The pass-through feature allows data to be passed from one
port to the other, in either direction. The PTX input must be
asserted to pass data from port X to port Y. The PTY will
likewise pass data from port Y to port X. A pass-through
operation takes precedence over a read operation.
For the case when AX and AY are the same, certain protocols
are followed. If both ports are read, the reads occur normally.
If one port is written and the other is read, the read from the
array will occur before the data is written. If both ports are
written, only the data on DQY will be written to the array.
The CY7C1301A operates from a +3.3V power supply. All
inputs and outputs are LVTTL-compatible. These dual I/O,
dual address synchronous SRAMs are well suited for ATM,
Ethernet switches, routers, cell/frame buffers, SNA switches
and shared memory applications.
The CY7C1301A device needs one extra cycle after power for
proper power on reset. The extra cycle is needed after V
CC
is
stable on the device. This device is available in a 176-pin
TQFP package.
Functional Description
The CY7C1301A SRAM integrates 262,144 x 36 SRAM cells
with advanced synchronous peripheral circuitry. It employs
high-speed, low-power CMOS designs using advanced
triple-layer polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two high-valued
resistors.
Logic Block Diagram
[1]
18/17
18/17
*AX
Address
Register
256K/128K x 9 x 4
SRAM Array
Address
Register
AY*
WEX#
Write X
Register
Write
Driver
Sensing
Amplifiers
Sensing
Amplifiers
Write
Driver
Write Y
Register
WEY#
PTX#
PTX
Register
Pass-Through
PTX
Register
PTY#
CLK
Data In
Register
Output
Register
Output
Register
Data In
Register
CLK
CE1X#
CE2X
Chip Enable
Register
Chip Enable
Register
DQX
DQY
Chip Enable
Register
Chip Enable
Register
CE1Y#
CE2Y
OEX#
OEY#
Note:
1. For 256 × 36 device, AX and AY are 18-bit-wide buses.
Cypress Semiconductor Corporation
Document # 38-05076 Rev. *C
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised January 19, 2003
CY7C1301A
.
Selection Guide
-100
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
5.0
500
140
-83
6.0
430
120
Unit
ns
mA
mA
Pin Configuration
176-pin TQFP
VSS
DQY19
DQX19
VSS
VCCQ
DQY18
DQX18
AX6
AY6
AX7
AY7
VSS
NC
NC
NC
VSS
NC
NC
CE2Y
CE1Y#
CLK
VCC
VSS
OEY#
OEX#
CE2X
CE1X#
WEY#
WEX#
PTY#
PTX#
AX8
AY8
AX9
AY9
AX17*
AY17*
DQX17
DQY17
VCC
VSS
DQX16
DQY16
VSS
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
VSS
DQX20
DQY20
VCCQ
VSS
DQX21
DQY21
DQX22
DQY22
VCCQ
VSS
DQX23
DQY23
DQX24
DQY24
VCCQ
VSS
DQX25
DQY25
DQX26
DQY26
VCC
VSS
DQY27
DQX27
DQY28
DQX28
VCCQ
VSS
DQY29
DQX29
DQY30
DQX30
VCCQ
VSS
DQY31
DQX31
DQY32
DQX32
VCCQ
VSS
DQY33
DQX33
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
VSS
DQX15
DQY15
VSS
VCCQ
DQX14
DQY14
DQX13
DQY13
VSS
VCCQ
DQX12
DQY12
DQX11
DQY11
VSS
VCCQ
DQX10
DQY10
DQX9
DQY9
VSS
VCC
DQY8
DQX8
DQY7
DQX7
VSS
VCCQ
DQY6
DQX6
DQY5
DQX5
VSS
VCCQ
DQY4
DQX4
DQY3
DQX3
VSS
VCCQ
DQY2
DQX2
VSS
Document # 38-05076 Rev. *C
VSS
DQY34
DQX34
VSS
VCCQ
DQY35
DQX35
VSS
VSS
AY5
AX5
AY4
AX4
AY3
AX3
AY2
AX2
AY1
AX1
AY0
AX0
VSS
VCC
AX10
AY10
AX11
AY11
AX12
AY12
AX13
AY13
AX14
AY14
AX15
AY15
AX16
AY16
DQX0
DQY0
VCCQ
VSS
DQX1
DQY1
VSS
Page 2 of 13
CY7C1301A
Pin Definitions (176-pin TQFP)
Pin Name
AX0–AX1
7
AY0–AY17
WEX
WEY
PTX
PTY
OEX
OEY
DQX0–
DQX35
DQY0–
DQY35
CLK
I/O
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input
Input
Input/
Output
Input/
Output
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Supply
Ground
Ground
I/O Supply
–
Pin Description
Synchronous Address Inputs of Port X:
Do not allow address pins to float.
Synchronous Address Inputs of Port Y:
Do not allow address pins to float.
Read Write of Port X:
WEX signal is a synchronous input that identifies whether the current
loaded cycle is a Read or Write operation.
Read Write of Port Y:
WEY signal is a synchronous input that identifies whether the current
loaded cycle is a Read or Write operation.
Pass-Through of Port X:
PTX signal is a synchronous input that enables passing Port X input
to Port Y output.
Pass-Through of Port Y:
PTY signal is a synchronous input that enables passing Port Y input
to Port X output.
Asynchronous Output Enable of Port X:
OEX must be LOW to read data. When OEX is
HIGH, the DQXx pins are in high-impedance state.
Asynchronous Output Enable of Port Y:
OEY must be LOW to read data. When OEY is
HIGH, the DQYx pins are in high-impedance state.
Data Inputs/Outputs of Port X:
Both the data input path and data output path are registered
and triggered by the rising edge of CLK.
Data Inputs/Outputs of Port Y:
Both the data input path and data output path are registered
and triggered by the rising edge of CLK.
Clock:
This is the clock input to this device. Except for OEX and OEY, all timing references
of the address, data in, and all control signals for the device are made with respect to the rising
edge of CLK.
Synchronous Active LOW Chip Enable Port X:
CE1X is used with CE2X to enable Port X
of this device. CE1X sampled HIGH at the rising edge of clock initiates a deselect cycle for
Port X.
Synchronous Active HIGH Chip Enable Port X:
CE2X is used with CE1X to enable Port X
of this device. CE2X sampled LOW at the rising edge of clock initiates a deselect cycle for
Port X.
Synchronous Active LOW Chip Enable Port Y:
CE1Y is used with CE2Y to enable Port Y
of this device. CE1Y sampled HIGH at the rising edge of clock initiates a deselect cycle for
Port Y.
Synchronous Active HIGH Chip Enable Port Y:
CE2Y is used with CE1Y to enable Port Y
of this device. CE2Y sampled LOW at the rising edge of clock initiates a deselect cycle for
Port Y.
Power Supply:
+3.3V –5% and +5%.
Ground:
GND.
Ground:
GND. No chip current flows through these pins. However, user needs to connect
GND to these pins. Pins 140 and 141 are V
SS
for 128K × 36 device.
Output Buffer Supply:
+3.3V –5% and +5%.
No Connect:
These signals are not internally connected. User can connect them to V
CC
, V
SS
,
or any signal lines or simply leave them floating.
CE1X
CE2X
CE1Y
CE2Y
V
CC
V
SS
V
SS
V
CCQ
NC
Document # 38-05076 Rev. *C
Page 3 of 13
CY7C1301A
Cycle Description Truth Table
[2, 3, 4, 5, 6, 7, 8, 9]
Operation
Deselect Cycle
Deselect Cycle
Write Port X
Write Port Y
Pass-through from X to Y
Pass-through from Y to X
Read Port X
Read Port Y
CE1X
H
X
L
X
L
L
L
X
CE2X
X
L
H
X
H
H
H
X
CE1Y
H
X
X
L
L
L
X
L
CE2Y
X
L
X
H
H
H
X
H
WEX
X
X
0
X
X
X
1
X
WEY
X
X
X
0
X
X
X
1
PTX
X
X
X
X
0
X
1
1
PTY
X
X
X
X
X
0
1
1
Notes:
2. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
3. All inputs except OEX and OEY must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK.
4. OEX and OEY must be asserted to avoid bus contention during Write and Pass-through cycles. For a Write and Pass-through operation following a READ
operation, OEX/OEY must be HIGH before the input data required set-up time plus High-Z time for OEX/OEY and staying HIGH throughout the input data
hold time.
5. Operation number 3–6 can be used in any combination.
6. Operation numbers 4 and 7, 3 and 8, and 7 and 8 can be combined.
7. Operation number 5 can not be combined with operation number 7 or 8 because Pass-through operations have higher priority over a Read operation.
8. Operation number 6 can not be combined with operation number 7 or 8 because Pass-through operations have higher priority over a Read operation.
9. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
Document # 38-05076 Rev. *C
Page 4 of 13
CY7C1301A
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature
..................................... −55°C
to +125°C
Ambient Temperature with
Power Applied....................................................
−10°C
to +85°C
Supply Voltage on V
DD
Relative to GND.........−0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State
[10]
....................................−0.5V
to V
CCQ
+ 0.5V
Range
Commercial
DC Input Voltage
[10]
................................ −0.5V
to V
CCQ
+ 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage .......................................... >1601V
(per MIL-STD-883, Method 3015)
Latch-Up Current ................................................... > 200 mA
Operating Range
Ambient
Temperature
[11]
0°C to +70°C
V
DD
/V
DDQ
(12)
3.3V ± 5%
Electrical Characteristics
Over the Operating Range
Parame-
ter
V
DD
V
DDQ
V
OH
V
OL
V
IH
V
IL
I
X
I
OZ
I
CC
I
SB
Description
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH
Voltage
[13]
Input LOW Voltage
[14]
Input Load Current
Output Leakage
Current
V
DD
Operating
Supply
Automatic CE
Power-Down
Current—CMOS
Inputs
GND
≤
V
IN
≤
V
DDQ
GND
≤
V
IN
≤
V
DDQ,
Output Disabled
V
DD
= Max., I
OUT
= 0 mA,
f = f
MAX
= 1/t
CYC
Max. V
DD
, Device Deselected ,
V
IN
≤
0.3V or V
IN
> V
DDQ
– 0.3V,
f=0
[15]
Test Conditions
Min.
3.135
3.135
Max.
3.465
3.465
0.4
Unit
V
V
V
V
V
V
µA
µA
mA
mA
mA
mA
V
DD
= Min., I
OH
= –4.0 mA
V
DD
= Min., I
OL
= 8.0 mA
2.4
2.0
−0.5
−5
−5
V
CC
+
0.5V
0.8
5
5
500
430
140
120
10.0 ns cycle 100 MHz
12.0 ns cycle 83 MHz
10.0 ns cycle100 MHzs
12.0 ns cycle 83MHz
Capacitance
[18]
Parameter
C
IN
C
CLK
C
I/O
Description
Input Capacitance
Clock Input Capacitance
Input/Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 3.3V,
V
CCQ
= 3.3V
Max.
8
9
8
Unit
pF
pF
pF
Notes:
10. Minimum voltage equals –2.0V for pulse duration less than 20 ns.
11. T
A
is the case temperature.
12. Power supply ramp up should be monotonic.
13. Overshoot: V
IH
≤
+6.0V for t
≤
t
KC /2
.
14. Undershoot:V
IL
≤
–2.0V for t
≤
t
KC /2
.
15. “Device Deselected” means the device is in Power-down mode as defined in the truth table.
16. Tested initially and after any design or process change that may affect these parameters.
Document # 38-05076 Rev. *C
Page 5 of 13
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