Ordering number : EN*5966
LC74793,
LC74793JM
Preliminary
Overview
CMOS IC
VPS / PDC Slicer IC
Package Dimensions
unit: mm
3067-DIP24S
[LC74793]
The LC74793/JM is a CMOS IC that provides PDS, VPS,
and UDT data acquisition functions. The LC74793/JM
supports microprocessor control of its operating modes
and microprocessor read out of data acquired in any of its
operating modes.
Features
• VPS data acquisition (5 or 11 to 15 bytes)
VPS: Video Program System
• PDC (8/30/2) data acquisition (13 to 25 bytes)
PDC: Program Delivery Control
• UDT (8/30/1) data acquisition (13 to 25 bytes)
UDT: Unified Date and Time
• Header (X/00) data acquisition (14 to 45 bytes)
• Status display (8/30/1, 8/30/2) data acquisition (26 to
45 bytes)
• Automatic VPS/PDC discrimination mode
• Built-in AFC and sync separator circuits
• Synchronization discrimination circuit
• I
2
C bus support
SANYO: DIP24S
unit: mm
3112-MFP24S
[LC74793JM]
SANYO: MFP24S
©
2011, SCILLC. All rights reserved.
Jan-2011, Rev. 0
www.onsemi.com
Publication Order Number:
LC74793_LC74793JM/D
LC74793, 74793JM
Pin Functions
Pin No.
1
2
3
4
5
6
Pin
V
SS
1
Xtalin
Xtalout
CTRL1
NC
SDA
Data I/O
I
2
C bus
Clock input
I
2
C bus
External synchronizing signal
discrimination output
Horizontal synchronizing signal output
Ground
Charge pump output
Oscillator control voltage input
Oscillator range adjustment
Data acquisition output
Power supply (+5 V)
Sync separator circuit input
Slice level output
Composite synchronizing signal output
Vertical synchronizing signal input
PDC/VPS data I/O.
I
2
C bus write address: 01111100
I
2
C bus read address: 01111101
PDC/VPS data clock input.
I
2
C bus
External synchronizing signal presence/absence discrimination status output.
A high level is output when synchronizing signals are present.
This pin outputs the crystal oscillator clock when the RST pin is low.
(This reset state output can be disabled with command input.)
Horizontal synchronizing signal output
Ground. (VCO circuit ground)
Charge pump output. Connect a low-pass filter to this pin.
VCO oscillation control voltage input
VCO oscillation range adjustment resistor connection
Outputs a low level when PDC/VPS data has been discriminated
Power supply (+5 V) (VCO system power supply)
Internal sync separator circuit video signal input
Slice level verification
Internal sync separator circuit composite synchronizing signal output
Inputs the vertical synchronizing signal by integrating the SEP out pin output signal.
Applications must connect the SEP out pin to this pin through an integration circuit. If
unused, connect this pin to VDD1. (This pin is enabled when CTRL2 is high.)
Vertical synchronizing signal output
This pin outputs the VCO clock when the RST pin is low.
(This reset state output can be disabled with command input.)
Controls whether or not the VSYNC vertical synchronizing signal is input to the SEPin
input.
When low: The VSYNC signal is not input. (The internal vertical separation circuit is used.)
When high: The VSYNC signal is input.
Connection for the clock phase adjustment resistor.
System reset input.
A pull-up resistor is built in. (This input has hysteresis characteristics.)
Power supply. (+5 V: digital system power supply)
Ground
Crystal oscillator connections
Crystal element switching
Function
Digital system ground
Connections for the crystal element and capacitors that form the crystal oscillator. Also
used for external clock input (fsc, 2fsc, or 4fsc).
Switches between external clock input mode and crystal oscillator mode. Set this pin low
for crystal oscillator, and high for external clock input.
Description
7
SCL
8
SYNC
JDG
Hout
VSS2
CP
OUT
VCO
IN
VCOR
DAV
V
DD
2
SYNin
SEPC
SEP
OUT
SEP
IN
9
10
11
12
13
14
15
16
17
18
19
20
Vout
Vertical synchronizing signal output
21
CTRL2
SEPin input control
22
23
24
CDLR
RST
V
DD
1
Clock phase adjustment
Reset input
Power supply (+5 V)
Rev.0 I Page 3 of 24 I www.onsemi.com
LC74793, 74793JM
Specifications
Absolute Maximum Ratings
Parameter
Supply voltage
Input voltage
Output voltage
Allowable power dissipation
Operating temperature
Storage temperature
Symbol
V
DD
V
IN
V
OUT
Pd max
Topr
Tstg
V
DD
1 and V
DD
2
All input pins
SDA, SYNCJDG, SEPOUT, DAV, HOUT, and VOUT
Ta = 25°C
Conditions
Ratings
V
SS
– 0.3 to V
SS
+ 7.0
V
SS
– 0.3 to V
DD
1 + 0.3
V
SS
– 0.3 to V
DD
1 + 0.3
350
–30 to +70
–40 to +125
Unit
V
V
V
mW
°C
°C
Recommended Operating Conditions
Parameter
Supply voltage
High-level input voltage
Symbol
V
DD
1
V
IH
1
V
IH
2
V
IH
3
Low-level input voltage
Pull-up resistance
Composite video signal input voltage
Input voltage
V
IL
1
V
IL
2
RPU
V
IN
1
V
IN
2
FOSC1
Oscillator frequency
FOSC2
FOSC3
V
DD
1 and V
DD
2
SDA and SCL
RST
CTRL1 and CTRL2
RST, SDA, and SCL
CTRL1 and CTRL2
RST
SYNIN
XtalIN (in external clock input mode)
fin = fsc, 2fsc, or 4fsc
V
DD
1 = 5 V
V
DD
1 = 5 V
Conditions
Ratings
min
4.5
0.8 V
DD
1
0.8 V
DD
1
0.7 V
DD
1
V
SS
– 0.3
V
SS
– 0.3
25
1.5
0.10
17.734
8.867
4.433
50
2.0
typ
5.0
max
5.5
5.5
V
DD
1 + 0.3
V
DD
1 + 0.3
0.2 V
DD
1
0.3 V
DD
1
90
2.25
5.0
Unit
V
V
V
V
V
V
kΩ
Vp-p
Vp-p
MHz
MHz
MHz
The XtalIN and XtalOUT oscillator pins (4fsc: PAL)
The XtalIN and XtalOUT oscillator pins (2fsc: PAL)
The XtalIN and XtalOUT oscillator pins (fsc: PAL)
Note: Note that adequate measure must be taken to prevent noise from entering the XtalIN pin when it is used in clock input mode.
Rev.0 I Page 4 of 24 I www.onsemi.com
LC74793, 74793JM
Electrical Characteristics
at Ta = –30 to +70°C, V
DD
1 = 5 V unless otherwise specified.
Parameter
Output off leakage current
High-level output voltage
Symbol
Ileak2
V
OH
1
V
OL
1
Low-level output voltage
V
OL
2
I
IH
Input current
I
IL
Operating current drain
I
DD
1
Applicable pins
SDA and DAV
SEPOUT, CPOUT, SYNCJDG,
HOUT, and VOUT
SEPOUT, CPOUT, SYNCJDG,
DAV, HOUT, and VOUT
SDA
V
DD
1 = 4.5 V,
I
OH
= –1.0 mA
V
DD
1 = 4.5 V
I
OL
= 1.0 mA
V
DD
1 = 5.0 V
I
OL
= 3.0 mA
3.5
1.0
0.4
1
–1
Conditions
Ratings
min
typ
max
1
Unit
μA
V
V
V
μA
μA
RST, SDA, SCL, CTRL1, CTRL2,
V
IN
= V
DD
1
VCOIN
SDA, SCL, CTRL1, CTRL2,
VCOIN
V
DD
1 and V
DD
2
V
IN
= V
SS
1
With all outputs open
and a 17.734 MHz
crystal
40
mA
Timing Characteristics
PDC and VPS Read and Write (I
2
C bus timing)
at Ta = –30 to +70°C, V
DD
1 = 5±0.5 V
Parameter
SCL frequency
Bus release time
Start hold time
SCL low-level period
SCL high-level period
Data hold time
Data setup time
Rise time
Fall time
Stop setup time
Symbol
f
SCL
t
BUF
t
HD
; STA
t
LOW
t
HIGN
t
HD
; DAT
t
SU
; DAT
t
R
t
F
t
SU
; STO
4.0
4.7
4.0
4.7
4.0
0
250
1000
300
Conditions
Ratings
min
typ
max
100
Unit
kHz
μs
μs
μs
μs
μs
ns
ns
ns
μs
Supplementary Documentation
• PDC and VPS serial timing (I
2
C bus timing)
S: Start condition
P: Stop condition
Rev.0 I Page 5 of 24 I www.onsemi.com
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