KAF-16803
4096 (H) x 4096 (V) Full
Frame CCD Image Sensor
Description
The KAF−16803 image sensor is a redesigned version of the
popular KAF−16801 image sensor (4096 (H)
×
4096 (V) pixel
resolution), with enhancements that specifically target the needs of
high performance digital radiography applications. Improvements
include enhanced quantum efficiency for improved DQE at higher
spatial frequencies, lower noise for improved contrast in areas of high
density, and anti-blooming protection to prevent image bleed from
over exposure in regions outside the patient.
The sensor utilizes the TRUESENSE Transparent Gate Electrode to
improve sensitivity compared to the use of a standard front side
illuminated polysilicon electrode, as well as microlenses to maximize
light sensitivity. When combined with large imaging area and small
pixel size, the KAF−16803 provides the sensitivity, resolution and
contrast necessary for high quality digital radiographs.
To simplify device integration, the KAF−16803 image sensor uses
the same pin-out and package as the KAF−16801 image sensor.
Table 1. GENERAL SPECIFICATIONS
Parameter
Architecture
Total Number of Pixels
Number of Effective Pixels
Number of Active Pixels
Pixel Size
Active Image Size
Typical Value
Full Frame CCD, Square Pixels
4145 (H)
×
4128 (V) = 17.1 Mp
4127 (H)
×
4128 (V) = 17.0 Mp
4096 (H)
×
4096 (V) = 16.8 Mp
9.0
mm
(H)
×
9.0
mm
(V)
36.8 mm (H)
×
36.8 mm (V)
52.1 mm Diagonal
645 1.3x Optical Format
1:1
1
100,000 electrons
22
mV/e
−
60%
28.7 V/mJ/cm
2
9 e
−
3 e
−
/pix/sec
6.3°C
80 dB
> 100 X Saturation Exposure
10 MHz
CERDIP (Sidebrazed, CuW)
AR Coated, 2 Sides and Taped Clear
www.onsemi.com
Figure 1. KAF−16803 CCD Image Sensor
Features
•
TRUESENSE Transparent Gate Electrode
•
•
•
•
•
for High Sensitivity
High Resolution
Large Image Area
High Quantum Efficiency
Low Noise Architecture
Board Dynamic Range
Aspect Ratio
Horizontal Outputs
Saturation Signal
Output Sensitivity
Quantum Efficiency (550 nm)
Responsivity (550 nm)
Read Noise (f = 4 MHz)
Dark Signal
Dark Current Doubling
Temperature
Linear Dynamic Range
(f = 4 MHz)
Blooming Protection
(4 ms Exposure Time)
Maximum Date Rate
Package
Cover Glass
Application
•
Medical
•
Scientific
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
NOTE: Parameters above are specified at T = 25°C unless otherwise noted.
©
Semiconductor Components Industries, LLC, 2015
1
December, 2015 − Rev. 2
Publication Order Number:
KAF−16803/D
KAF−16803
ORDERING INFORMATION
Table 2. ORDERING INFORMATION − KAF−16803 IMAGE SENSOR
Part Number
KAF−16803−ABA−DD−BA
KAF−16803−ABA−DD−AE
KAF−16803−ABA−DP−BA
KAF−16803−ABA−DP−AE
Description
Monochrome, Microlens, CERDIP Package (Sidebrazed, CuW),
AR Coated 2 Sides, Standard Grade
Monochrome, Microlens, CERDIP Package (Sidebrazed, CuW),
AR Coated 2 Sides, Engineering Sample
Monochrome, Microlens, CERDIP Package (Sidebrazed, CuW),
Taped Clear Cover Glass, Standard Grade
Monochrome, Microlens, CERDIP Package (Sidebrazed, CuW),
Taped Clear Cover Glass, Engineering Sample
Marking Code
KAF−16803−ABA
Serial Number
See the ON Semiconductor
Device Nomenclature
document (TND310/D) for a full description of the naming convention
used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.
www.onsemi.com
2
KAF−16803
DEVICE DESCRIPTION
Architecture
1 Test Row
V1
V2
9
1
4 13
LOD
20 1
KAF−16803
4096 (H)
×
4096 (V)
9.0
×
9.0
mm
Pixels
1 9 12 6
OG
RD
RG
VDD
VOUT
VSS
SUB
1 6 4 1 3
20 1
1
20 Dark
4096
1 9 12
H1
H2
Figure 2. Block Diagram
Each line is composed of dummy pixels, internal test
pixels, active buffer pixels, and valid photoactive pixels.
Dummy Pixels
Within each horizontal shift register the first pixels are 11
dummy pixels and should not be used to determine a dark
reference level.
Internal Test
The next 4 pixels are introduced into the design to
facilitate production testing. These behave differently than
the buffer and dark pixels and should not be used to establish
a dark reference. The last three pixels in each line are also
internal test pixels and should not be used to establish a dark
reference.
Dark Reference Pixels
Surrounding the periphery of the device is a border of light
shielded pixels creating a dark region. Within this dark
region, exist light shielded pixels that include 20 leading
dark pixels on every line. There are also 20 full dark lines at
the start and 9 full dark lines at the end of every frame. Under
normal circumstances, these pixels do not respond to light
and may be used as a dark reference.
Active Buffer Pixels
There is 1 photoactive buffer row and column adjacent to
the valid photoactive pixels. These may have signals levels
different from those in the imaging array and are not counted
in the active pixel count.
Image Acquisition
An electronic representation of an image is formed when
incident photons falling on the sensor plane create
electron-hole pairs within the device. These photon-induced
electrons are collected locally by the formation of potential
wells at each pixel site. The number of electrons collected is
linearly dependent on light level and exposure time and
non-linearly dependent on wavelength. When the pixel’s
capacity is reached, excess electrons are discharged into the
lateral overflow drain to prevent crosstalk or ‘blooming’.
During the integration period, the V1 and V2 register clocks
are held at a constant (low) level.
Charge Transport
The integrated charge from each pixel is transported to the
output using a two-step process. Each line (row) of charge
is first transported from the vertical CCDs to a horizontal
CCD register using the V1 and V2 register clocks.
The horizontal CCD is presented a new line on the falling
edge of V2 while H1 is held high. The horizontal CCDs then
transport each line, pixel by pixel, to the output structure by
alternately clocking the H1 and H2 pins in a complementary
fashion.
www.onsemi.com
3
KAF−16803
Horizontal Register
Output Structure
H2
H1
HCCD
Charge
Transfer
VDD
OG
RG
RD
Floating
Diffusion
VOUT
VSS
Source
Follower
#1
Source
Follower
#2
Source
Follower
#3
Figure 3. Output Architecture
The output consists of a floating diffusion capacitance
connected to a three-stage source follower. Charge
presented to the floating diffusion (FD) is converted into
a voltage and is current amplified in order to drive off-chip
loads. The resulting voltage change seen at the output is
linearly related to the amount of charge placed on the FD.
Once the signal has been sampled by the system electronics,
the reset gate (RG) is clocked to remove the signal and FD
is reset to the potential applied by reset drain (RD).
Increased signal at the floating diffusion reduces the voltage
seen at the output pin. To activate the output structure, an
off-chip current source must be added to the VOUT pin of
the device. See Figure 4.
www.onsemi.com
4
KAF−16803
Output Load
VDD = +15 V
I
OUT
= |5 mA|
VOUT
0.1
mF
2N3904 or
Equivalent
Buffered
Video
Output
1 kW
140
W
NOTE: Component values may be revised based on operating conditions and other design considerations.
Figure 4. Recommended Output Structure Load Diagram
www.onsemi.com
5
淘e淘
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
