HM514265C Series
HM51S4265C Series
262,144-word
×
16-bit Dynamic Random Access Memory
ADE-203-309A (Z)
Rev. 1.0
Jul. 21, 1995
Description
The Hitachi HM51(S)4265C is a CMOS dynamic RAM organized 262,144-word
×
16-bit.
HM51(S)4265C has realized higher density, higher performance and various functions by employing 0.8
µm
CMOS process technology and some new CMOS circuit design technologies. The HM51(S)4265C
offers Extended Data Out (EDO) Page Mode as a high speed access mode. Multiplexed address input
permits the HM51(S)4265C to be packaged in standard 400-mil 40-pin plastic SOJ and standard 400-mil
44-pin plastic TSOPII. Internal refresh timer enables HM51S4265C self reflesh operation.
Features
•
•
•
Single 5 V (±10%) (HM51(S)4265C-6/7/8)
(±5%) (HM51(S)4265C-6R)
High speed
— Access time: 60 ns/70 ns/80 ns (max)
Low power dissipation
— Active mode: 825 mW/788 mW/770 mW/688 mW (max)
— Standby mode: 11 mW (max) (HM51(S)4265C-6/7/8)
10.5 mW (max) (HM51(S)4265C-6R)
1.1 mW (max) (L-version) (HM51(S)4265CL-6/7/8)
1.05 mW (max) (L-version) (HM51(S)4265CL-6R)
EDO page mode capability
512 refresh cycles : 8 ms
128 ms (L-version)
2 variations of refresh
—
RAS
-only refresh
—
CAS
-before-
RAS
refresh
2
CAS
-byte control
Battery backup operation (L-version)
Self refresh operation (HM51S4265C)
•
•
•
•
•
•
HM514265C, HM51S4265C Series
Ordering Information
Type No.
HM514265CJ-6
HM514265CJ-6R
HM514265CJ-7
HM514265CJ-8
HM514265CLJ-6
HM514265CLJ-6R
HM514265CLJ-7
HM514265CLJ-8
HM51S4265CJ-6
HM51S4265CJ-6R
HM51S4265CJ-7
HM51S4265CJ-8
HM51S4265CLJ-6
HM51S4265CLJ-6R
HM51S4265CLJ-7
HM51S4265CLJ-8
HM514265CTT-6
HM514265CTT-6R
HM514265CTT-7
HM514265CTT-8
HM514265CLTT-6
HM514265CLTT-6R
HM514265CLTT-7
HM514265CLTT-8
HM51S4265CTT-6
HM51S4265CTT-6R
HM51S4265CTT-7
HM51S4265CTT-8
HM51S4265CLTT-6
HM51S4265CLTT-6R
HM51S4265CLTT-7
HM51S4265CLTT-8
Access time
60 ns
60 ns
70 ns
80 ns
60 ns
60 ns
70 ns
80 ns
60 ns
60 ns
70 ns
80 ns
60 ns
60 ns
70 ns
80 ns
60 ns
60 ns
70 ns
80 ns
60 ns
60 ns
70 ns
80 ns
60 ns
60 ns
70 ns
80 ns
60 ns
60 ns
70 ns
80 ns
400-mil 44-pin plastic TSOPII (TTP-44/40DB)
Package
400-mil 40-pin plastic SOJ (CP-40DA)
2
HM514265C, HM51S4265C Series
Pin Arrangement
HM514265CJ/CLJ Series
HM51S4265CJ/CLJ Series
V
CC
I/O0
I/O1
I/O2
I/O3
V
CC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
SS
I/O15
I/O14
I/O13
I/O12
V
SS
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
V
SS
HM514265CTT/CLTTSeries
HM51S4265CTT/CLTTSeries
V
CC
I/O0
I/O1
I/O2
I/O3
V
CC
I/O4
I/O5
I/O6
I/O7
1
2
3
4
5
6
7
8
9
10
44
43
42
41
40
39
38
37
36
35
V
SS
I/O15
I/O14
I/O13
I/O12
V
SS
I/O11
I/O10
I/O9
I/O8
(Top view)
NC
NC
WE
RAS
NC
A0
A1
A2
A3
V
CC
13
14
15
16
17
18
19
20
21
22
32
31
30
29
28
27
26
25
24
23
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
V
SS
(Top view)
Pin Description
Pin name
A0
–A8
Function
Address input
—
Row address
—
Column address
—
Refresh address
Data-in/data-out
Row address strobe
Column address strobe
Read/write enable
Output enable
Power (+5 V)
Ground
No connection
A0
–
A8
A0
–
A8
A0
–
A8
I/O0
–
I/O15
RAS
UCAS, LCAS
WE
OE
V
CC
V
SS
NC
3
HM514265C, HM51S4265C Series
Block Diagram
I/O Bus & Column Decoder
I/O Bus & Column Decoder
I/O Bus & Column Decoder
I/O Bus & Column Decoder
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
Row
Decoder
Row
Row
Decoder
Decoder
Row
Decoder
Row
Decoder
Row
Row
Decoder
Decoder
Row
Decoder
Selector
Selector
Selector
Selector
I/O4
I/O4
Buffer
I/O5
Buffer
I/O6
Buffer
I/O7
Buffer
256 k Memory Array Mat
I/O11
Buffer
Peripheral Circuit
I/O3
I/O3
Buffer
I/O2
I/O2
Buffer
I/O1
I/O1
Buffer
I/O0
I/O0
Buffer
I/O15
I/O15
Buffer
I/O14
I/O14
Buffer
I/O13
I/O13
Buffer
I/O12
I/O12
Buffer
I/O11
I/O5
I/O10
I/O10
Buffer
I/O9
Buffer
I/O8
Buffer
I/O9
I/O6
I/O7
I/O8
Peripheral Circuit
WE
RAS
Address
A0,A1,A2,A3
Address A4,A5
A6,A7,A8
LCAS
UCAS
OE
Selector
Row
Decoder
Selector
Row
Decoder
Selector
Row
Decoder
Selector
Row
Decoder
Row
Row
Decoder
Decoder
Row
Row
Decoder
Decoder
I/O Bus & Column Decoder
I/O Bus & Column Decoder
I/O Bus & Column Decoder
I/O Bus & Column Decoder
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
Operation Mode
The HM51(S)4265C series has the following 11 operation modes.
4
256 k Memory Array Mat
Peripheral Circuit
HM514265C, HM51S4265C Series
1. Read cycle
2. Early write cycle
3. Delayed write cycle
4. Read-modify-write cycle
5.
6.
RAS
-only refresh cycle
CAS
-before-
RAS
refresh cycle
7. Self refresh cycle (HM51S4265C)
8. EDO page mode read cycle
9. EDO page mode early write cycle
10. EDO page mode delayed write cycle
11. EDO page mode read- modify-write cycle
Inputs
RAS
H
H
L
L
L
L
L
H to L
LCAS
H
L
L
L
L
L
H
H
L
L
L
L
L
L
L
H to L
H to L
H to L
H to L
L
UCAS
H
L
L
L
L
L
H
L
H
L
H to L
H to L
H to L
H to L
L
H
L
*2
L
*2
H to L
H
L
D
H
L to H
H
Valid
Open
Undefined
Valid
Open
EDO page mode read cycle
EDO page mode early write cycle
EDO page mode delayed write cycle
EDO page mode read-modify-write cycle
Read cycle (Output disabled)
WE
D
H
H
L
*2
L
*2
H to L
D
D
OE
D
L
L
D
H
L to H
D
D
Output
Open
Valid
Valid
Open
Undefined
Valid
Open
Open
Operation
Standby
Standby
Read cycle
Early write cycle
Delayed write cycle
Read-modify-write cycle
RAS-only
refresh cycle
CAS-before-RAS
refresh cycle
Self refresh cycle (HM51S4265C)
Notes: 1. H: High(inactive) L: Low(active) D: H or L
2. t
WCS
≥
0 ns
Early write cycle
t
WCS
< 0 ns
Delayed write cycle
3. Mode is determined by the OR function of the
UCAS
and
LCAS.
(Mode is set by the earliest of
UCAS
and
LCAS
active edge and reset by the latest of
UCAS
and
LCAS
inactive edge.)
However write OPERATION and output HIZ control are done independently by each
UCAS,
LCAS.
ex. if
RAS
= H to L,
LCAS
= L,
UCAS
= H, then
CAS-before-RAS
refresh cycle is selected.
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