• Available in Pb-free and non Pb-free 44-pin 400-mil-
SOJ, 44-pin TSOP II and 48-ball FBGA packages
Functional Description
[1]
The CY7C1041CV33 is a high-performance CMOS Static
RAM organized as 262,144 words by 16 bits.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte LOW Enable
(BLE) is LOW, then data from I/O pins (I/O
0
–I/O
7
), is written
into the location specified on the address pins (A
0
–A
17
). If Byte
HIGH Enable (BHE) is LOW, then data from I/O pins
(I/O
8
–I/O
15
) is written into the location specified on the
address pins (A
0
–A
17
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte LOW Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
0
– I/O
7
. If Byte HIGH Enable (BHE) is
LOW, then data from memory will appear on I/O
8
to I/O
15
. See
the truth table at the back of this data sheet for a complete
description of Read and Write modes.
The input/output pins (I/O
0
–I/O
15
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a Write operation
(CE LOW, and WE LOW).
The CY7C1041CV33 is available in a standard 44-pin
400-mil-wide body width SOJ and 44-pin TSOP II package
with center power and ground (revolutionary) pinout, as well
as a 48-ball fine-pitch ball grid array (FBGA) package.
Logic Block Diagram
INPUT BUFFER
Pin Configuration
SOJ/
TSOP II
Top View
A
0
A
1
A
2
A
3
A
4
CE
I/O
0
I/O
1
I/O
2
I/O
3
V
CC
V
SS
I/O
4
I/O
5
I/O
6
I/O
7
WE
A
5
A
6
A
7
A
8
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
256K × 16
ARRAY
I/O
0
–I/O
7
I/O
8
–I/O
15
COLUMN
DECODER
BHE
WE
CE
OE
BLE
A
17
A
16
A
15
OE
BHE
BLE
I/O
15
I/O
14
I/O
13
I/O
12
V
SS
V
CC
I/O
11
I/O
10
I/O
9
I/O
8
NC
A
14
A
13
A
12
A
11
A
10
ROW DECODER
Notes:
1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com.
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
SENSE AMPS
Cypress Semiconductor Corporation
Document #: 38-05134 Rev. *H
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised September 1, 2006
CY7C1041CV33
Selection Guide
-10
Maximum Access Time
Maximum Operating Current
Commercial
Industrial
Automotive-A
Automotive-E
Maximum CMOS Standby Current
Commercial/
Industrial
Automotive-A
Automotive-E
10
10
15
10
10
10
90
100
100
-12
12
85
95
-15
15
80
90
-20
20
75
85
85
90
10
Unit
ns
mA
mA
mA
mA
mA
mA
mA
Pin Configurations
48-ball FBGA
(Top View)
1
BLE
I/O
0
I/O
1
V
SS
V
CC
I/O
6
I/O
7
NC
2
OE
BHE
I/O
2
I/O
3
I/O
4
I/O
5
NC
A
8
3
A
0
A
3
A
5
A
17
NC
A
14
A
12
A
9
4
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
CE
6
NC
I/O
8
A
B
C
D
E
F
G
H
I/O
10
I/O
9
I/O
11
I/O
12
I/O
13
WE
A
11
V
CC
V
SS
I/O
14
I/O
15
NC
Document #: 38-05134 Rev. *H
Page 2 of 12
CY7C1041CV33
Pin Definitions
Pin Name
A
0
–A
17
44-SOJ,
44-TSOP
Pin Number
1–5, 18–27,
42–44
48-ball FBGA
Pin Number
A3, A4, A5, B3,
B4, C3, C4, D4,
H2, H3, H4, H5,
G3, G4, F3, F4,
E4, D3
B1, C1, C2, D2,
E2, F2, F1, G1,
B6, C6, C5, D5,
E5, F5, F6, G6
A6, E3, G2, H1,
H6
G5
I/O Type
Input
Description
Address Inputs used to select one of the address
locations.
I/O
0
–I/O
15
7–10,13–16,
29–32, 35–38
Input/Output
Bidirectional Data I/O lines.
Used as input or output lines
depending on operation
NC
WE
28
17
No Connect
No Connects.
This pin is not connected to the die
Input/Control
Write Enable Input, active LOW.
When selected LOW, a
WRITE is conducted. When selected HIGH, a READ is
conducted.
Input/Control
Chip Enable Input, active LOW.
When LOW, selects the chip.
When HIGH, deselects the chip.
Input/Control
Byte Write Select Inputs, active LOW.
BHE controls
I/O
15
–I/O
8
, BLE controls I/O
7
–I/O
0
Input/Control
Output Enable, active LOW.
Controls the direction of the I/O
pins. When LOW, the I/O pins are allowed to behave as
outputs. When deasserted HIGH, I/O pins are tri-stated, and
act as input data pins.
Ground
Ground for the device.
Should be connected to ground of the
system.
CE
BHE, BLE
OE
6
40, 39
41
B5
B2, A1
A2
V
SS
V
CC
12, 34
11, 33
D1, E6
D6, E1
Power Supply
Power Supply inputs to the device.
Document #: 38-05134 Rev. *H
Page 3 of 12
CY7C1041CV33
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on V
CC
to Relative GND
[2]
.... –0.5V to +4.6V
DC Voltage Applied to Outputs
in High-Z State
[2]
....................................–0.5V to V
CC
+ 0.5V
DC Input Voltage
[2]
.................................–0.5V to V
CC
+ 0.5V
Current into Outputs (LOW) .........................................20 mA
Latch-up Current...................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Automotive-A
Automotive-E
Ambient
Temperature
0°C to +70°C
–40°C to +85°C
–40°C to +85°C
–40°C to +125°C
V
CC
3.3V ± 0.3V
DC Electrical Characteristics
Over the Operating Range
-10
Parameter
V
OH
V
OL
V
IH
V
IL[2]
I
IX
Description
Test Conditions
Min. Max.
2.4
0.4
2.0
–0.3
GND < V
I
< V
CC
Com’l/Ind’l
Auto-A
Auto-E
I
OZ
Output Leakage
Current
GND < V
OUT
< V
CC
, Com’l/Ind’l
Output Disabled
Auto-A
Auto-E
I
CC
V
CC
Operating
Supply Current
V
CC
= Max.,
f = f
MAX
= 1/t
RC
Com’l
Ind’l
Auto-A
Auto-E
I
SB1
Max. V
CC
,
Automatic CE
Com’l/Ind’l
Power-down Current CE > V
IH
Auto-A
—TTL Inputs
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
Auto-E
Max. V
CC
,
Automatic CE
Com’l/Ind’l
Power-down Current CE > V
CC
– 0.3V,
Auto-A
—CMOS Inputs
V
IN
> V
CC
– 0.3V,
or V
IN
< 0.3V, f = 0 Auto-E
40
40
10
10
10
10
40
40
90
100
100
85
95
80
90
–1
–1
+1
+1
–1
+1
–1
+1
–1
–1
V
CC
+ 0.3
0.8
+1
+1
2.0
–0.3
–1
Output HIGH Voltage V
CC
= Min., I
OH
= –4.0 mA
Output LOW Voltage V
CC
= Min., I
OL
= 8.0 mA
Input HIGH Voltage
Input LOW Voltage
Input Leakage
Current
2.4
0.4
V
CC
+ 0.3
0.8
+1
2.0
–0.3
–1
-12
Min.
Max.
2.4
0.4
V
CC
+ 0.3
0.8
+1
2.0
–0.3
–1
–1
–20
–1
–1
–20
-15
Min.
Max.
2.4
0.4
V
CC
+ 0.3
0.8
+1
+1
+20
+1
+1
+20
75
85
85
90
40
40
45
10
10
15
-20
Min.
Max. Unit
V
V
V
V
µA
µA
µA
µA
µA
µA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
I
SB2
Capacitance
[3]
Parameter
C
IN
C
OUT
Description
Input Capacitance
I/O Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz, V
CC
= 3.3V
Max.
8
8
Unit
pF
pF
Notes:
2. V
IL
(min.) = –2.0V and V
IH
(max) = V
CC
+ 0.5V for pulse durations of less than 20 ns.
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05134 Rev. *H
Page 4 of 12
CY7C1041CV33
Thermal Resistance
[3]
Parameter
Description
Test Conditions
TSOP-II
42.96
10.75
FBGA
38.15
9.15
SOJ
25.99
18.8
Unit
°C/W
°C/W
Θ
JA
Θ
JC
Thermal Resistance (Junction to Ambient) Test conditions follow standard
Thermal Resistance (Junction to Case) test methods and procedures for
measuring thermal impedance,
per EIA / JESD51.
AC Test Loads and Waveforms
[4]
10-ns Devices
OUTPUT
50
Ω
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
1.5V
Z = 50Ω
12-, 15-, 20-ns Devices
3.3V
R 317Ω
30 pF*
OUTPUT
30 pF
R2
351Ω
High-Z Characteristics
R 317Ω
(a)
ALL INPUT PULSES
(b)
3.3V
OUTPUT
5 pF
R2
351Ω
3.0V
90%
GND
10%
90%
10%
Rise Time: 1 V/ns
(c)
Fall Time: 1 V/ns
(d)
AC Switching Characteristics
[5]
Over the Operating Range
-10
Parameter
Read Cycle
t
power[6]
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
V
CC
(typical) to the first access
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
OE HIGH to High-Z
[7, 8]
CE LOW to Low-Z
[8]
CE HIGH to High-Z
[7, 8]
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low-Z
Byte Disable to High-Z
0
6
0
10
5
0
6
3
5
0
12
6
0
7
0
5
3
6
0
15
7
0
8
3
10
5
0
6
3
7
0
20
8
100
10
10
3
12
6
0
7
3
8
100
12
12
3
15
7
0
8
100
15
15
3
20
8
100
20
20
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
Min.
-12
Max.
Min.
-15
Max.
Min.
-20
Max.
Unit
Notes:
4. AC characteristics (except High-Z) for 10-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the Thevenin load
shown in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d).
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
6. t
POWER
gives the minimum amount of time that the power supply should be at typical V
CC
values until the first memory access can be performed.
7. t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured
±500
mV from steady-state voltage
8. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
9. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of
either of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the
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