MBM29DL640F
60/70
The device is organized into four physical banks : Bank A, Bank B, Bank C and Bank D, which can be considered
to be four separate memory arrays as far as certain operations are concerned. This device is the almost identical
to Fujitsu’s standard 3 V only Flash memories, with the additional capability of allowing a normal non-delayed
read access from a non-busy bank of the array while an embedded write (either a program or an erase) operation
is simultaneously taking place on the other bank.
The new design concept called FlexBank
TM
*
1
Architecture is implemented. With this concept the device can
execute simultaneous operation between Bank 1, a bank chosen from among the four banks, and Bank 2, a
bank consisting of the three remaining banks. This means that any bank can be chosen as Bank 1. (Refer to
FUNCTIONAL DESCRIPTION for Simultaneous Operation.)
The standard device offers access times 60 ns and 70 ns, allowing operation of high-speed
microprocessors without the wait. To eliminate bus contention the device has separate chip enable (CE) , write
enable (WE) and output enable (OE) controls.
This device consists of pin and command set compatible with JEDEC standard E
2
PROMs. Commands are
written to the command register using standard microprocessor write timings. Register contents serve as input
to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and erase operations. Reading data out of the device is
similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.
The device is programmed by executing the program command sequence. This invokes the Embedded Program
Algorithm
TM
which is an internal algorithm that automatically times the program pulse widths and verifies proper
cell margin. Typically each sector can be programmed and verified in about 0.5 seconds. Erase is accomplished
by executing the erase command sequence. This invokes the Embedded Erase Algorithm
TM
which is an internal
algorithm that automatically preprograms the array if it is not already programmed before executing the erase
operation. During erase, the device automatically times the erase pulse widths and verifies the proper cell margin.
Typically one sector is erased and verified in 0.2 second (if already completely preprogrammed) .
The device also features sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The device is erased when shipped from the factory.
The device features single 3.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low V
CC
detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ
7
,
by the Toggle Bit feature on DQ
6
, or the RY/BY output pin. Once a program or erase cycle is completed, the
device internally resets to the read mode.
The device also has a hardware RESET pin. When this pin is driven low, execution of any Embedded Program
Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the read
mode. The RESET pin may be tied to the system reset circuitry. Therefore if a system reset occurs during the
Embedded Program
TM
*
2
Algorithm or Embedded Erase
TM
*
2
Algorithm, the device is automatically reset to the
read mode and have erroneous data stored in the address locations being programmed or erased. These
locations need rewriting after the reset. Resetting the device enables the system’s microprocessor to read the
boot-up firmware from the Flash memory.
Fujitsu Flash technology combines years of EPROM and E
2
PROM experience to produce the highest levels of
quality, reliability, and cost effectiveness. The device memory electrically erases the entire chip or all bits within
a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a
time using the EPROM programming mechanism of hot electron injection.
*1 : FlexBank
TM
is a trademark of Fujitsu Limited.
*2 : Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc.
2
MBM29DL640F
60/70
s
FEATURES
•
0.16
µ
m Process Technology
•
Simultaneous Read/Write Operations (Dual Bank)
•
FlexBank
TM
*
1
Bank A : 8 Mbit (8 KB
×
8 and 64 KB
×
15)
Bank B : 24 Mbit (64 KB
×
48)
Bank C : 24 Mbit (64 KB
×
48)
Bank D : 8 Mbit (8 KB
×
8 and 64 KB
×
15)
Two virtual Banks are chosen from the combination of four physical banks (Refer to “sFUNCTIONAL DE-
SCRIPTION FlexBank
TM
Architecture”and “Example of Virtual Banks Combination”.)
Host system can program or erase in one bank, and then read immediately and simultaneously from the other
bank with zero latency between read and write operations.
Read-while-erase
Read-while-program
•
Single 3.0 V Read, Program, and Erase
Minimized system level power requirements
•
Compatible with JEDEC-standard Commands
Uses the same software commands as E
2
PROMs
•
Compatible with JEDEC-standard Worldwide Pinouts
48-pin TSOP (I) (Package suffix : TN
−
Normal Bend Type, TR
−
Reversed Bend Type)
48-ball FBGA (Package suffix : PBT)
• Minimum 100,000 Program/Erase Cycles
•
High Performance
60 ns maximum access time
•
Sector Erase Architecture
Sixteen 4 Kword and one hundred twenty-six 32 Kword sectors in word mode
Sixteen 8 Kbyte and one hundred twenty-six 64 Kbyte sectors in byte mode
Any combination of sectors can be concurrently erased. Also supports full chip erase.
•
HiddenROM
*
3
Region
256 byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
•
WP/ACC Input Pin
At V
IL
allows protection of “outermost” 2
×
8 Kbytes on both ends of boot sectors, regardless of sector protection/
unprotection status
At V
IH
, allows removal of boot sector protection
At V
ACC
, increases program performance
•
Embedded Erase
TM
*
2
Algorithms
Automatically preprograms and erases the chip or any sector
•
Embedded Program
TM
*
2
Algorithms
Automatically writes and verifies data at specified address
*1 : FlexBank
TM
is a trademark of Fujitsu Limited
*2 : Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc.
*3 : HiddenROM
TM
is a trademark of Fujitsu Limited.
(Continued)
3
MBM29DL640F
60/70
(Continued)
•
Data Polling and Toggle Bit feature for program detection or erase cycle completion
•
Ready/Busy Output (RY/BY)
Hardware method for detection of program or erase cycle completion
•
Automatic Sleep Mode
When addresses remain stable, the device automatically switches itself to low power mode.
•
Low V
CC
Write Inhibit
≤
2.5 V
•
Program Suspend/Resume
Suspends the program operation to allow a read in another byte
•
Erase Suspend/Resume
Suspends the erase operation to allow a read data and/or program in another sector within the same device
•
Sector Group Protection
Hardware method disables any combination of sector groups from program or erase operations
• Sector Group Protection Set function by Extended sector group protection command
•
Fast Programming Function by Extended Command
•
Temporary Sector Group Unprotection
Temporary sector group unprotection via the RESET pin.
•
In accordance with CFI (Common Flash Memory Interface)
4
PCB设计
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
