KAI-02050
1600 (H) x 1200 (V) Interline
CCD Image Sensor
Description
The KAI−02050 Image Sensor is a 2−megapixel CCD in a 2/3″
optical format. Based on the TRUESENSE 5.5 micron Interline
Transfer CCD Platform, the sensor features broad dynamic range,
excellent imaging performance, and a flexible readout architecture
that enables use of 1, 2, or 4 outputs for full resolution readout up to 68
frames per second. A vertical overflow drain structure suppresses
image blooming and enables electronic shuttering for precise exposure
control. Other features include low dark current, negligible lag, and
low smear.
The sensor shares common PGA pin-out and electrical
configurations with other devices based on the TRUESENSE
5.5 micron Interline Transfer CCD Platform, allowing a single camera
design to support multiple members of this sensor family.
Table 1. GENERAL SPECIFICATIONS
Parameter
Architecture
Total Number of Pixels
Number of Effective Pixels
Number of Active Pixels
Pixel Size
Active Image Size
Aspect Ratio
Number of Outputs
Charge Capacity
Output Sensitivity
Quantum Efficiency
Mono (−ABA)
R, G, B (−FBA)
R, G, B (−CBA)
Read Noise (f = 40 MHz)
Dark Current
Photodiode / VCCD
Dark Current Doubling Temp
Photodiode / VCCD
Dynamic Range
Charge Transfer Efficiency
Blooming Suppression
Smear
Image Lag
Maximum Pixel Clock Speed
Maximum Frame Rates
Quad / Dual / Single Output
Package
Cover Glass
Typical Value
Interline CCD, Progressive Scan
1684 (H)
×
1264 (V)
1640 (H)
×
1240 (V)
1600 (H)
×
1200 (V)
5.5
mm
(H)
×
5.5
mm
(V)
8.8 mm (H)
×
6.6 mm (V)
11.0 mm (diagonal), 2/3″ Optical Format
4:3
1, 2, or 4
20,000 electrons
34
mV/e
−
44%
29%, 37%, 39%
31%, 37%, 38%
12 e
−
rms
7 / 100 e
−
/s
7°C / 9°C
64 dB
0.999999
> 300 X
−100
dB
< 10 electrons
40 MHz
68 / 34 / 18 fps
68 Pin PGA
64 Pin CLCC
AR Coated, 2-Sides or Clear Glass
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Figure 1. KAI−02050 Interline CCD
Image Sensor
Features
•
•
•
•
•
•
•
•
Color or Monochrome Configurations
Progressive Scan Readout
Flexible Readout Architecture
High Frame Rate
High Sensitivity
Low Noise Architecture
Excellent Smear Performance
Package Pin Reserved for Device
Identification
Applications
•
Industrial Imaging
•
Medical Imaging
•
Security
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
NOTE: All Parameters are specified at T = 40°C unless otherwise noted.
©
Semiconductor Components Industries, LLC, 2015
August, 2015
−
Rev. 8
1
Publication Order Number:
KAI−02050/D
KAI−02050
ORDERING INFORMATION
Standard Devices
See full datasheet for ordering information associated with devices no longer recommended for new designs.
Table 2. ORDERING INFORMATION
−
STANDARD DEVICES
Part Number
KAI−02050−AAA−JP−BA
KAI−02050−AAA−JP−AE
KAI−02050−ABA−JD−BA
KAI−02050−ABA−JD−AE
KAI−02050−ABA−JP−BA
KAI−02050−ABA−JP−AE
KAI−02050−ABA−FD−BA
KAI−02050−ABA−FD−AE
KAI−02050−FBA−JD−BA
KAI−02050−FBA−JD−AE
KAI−02050−FBA−FD−BA
KAI−02050−FBA−FD−AE
KAI−02050−FBA−JB−B2
KAI−02050−FBA−JB−AE
KAI−02050−FBA−JB−B2−T
Description
Monochrome, No Microlens, PGA Package, Taped Clear Cover Glass, No
Coatings, Standard Grade.
Monochrome, No Microlens, PGA Package, Taped Clear Cover Glass, No
Coatings, Engineering Grade.
Monochrome, Telecentric Microlens, PGA Package, Sealed Clear Cover Glass
with AR Coating (Both Sides), Standard Grade.
Monochrome, Telecentric Microlens, PGA Package, Sealed Clear Cover Glass
with AR Coating (Both Sides), Engineering Grade.
Monochrome, Telecentric Microlens, PGA Package, Taped Clear Cover Glass,
No Coatings, Standard Grade.
Monochrome, Telecentric Microlens, PGA Package, Taped Clear Cover Glass,
No Coatings, Engineering Grade.
Monochrome, Telecentric Microlens, CLCC Package, Sealed Clear Cover Glass
with AR Coating (Both Sides), Standard Grade.
Monochrome, Telecentric Microlens, CLCC Package, Sealed Clear Cover Glass
with AR Coating (Both Sides), Engineering Grade.
Gen2 Color (Bayer RGB), Telecentric Microlens, PGA Package, Sealed Clear
Cover Glass with AR Coating (Both Sides), Standard Grade.
Gen2 Color (Bayer RGB), Telecentric Microlens, PGA Package, Sealed Clear
Cover Glass with AR Coating (Both Sides), Engineering Grade.
Gen2 Color (Bayer RGB), Telecentric Microlens, CLCC Package, Sealed Clear
Cover Glass with AR Coating (Both Sides), Standard Grade.
Gen2 Color (Bayer RGB), Telecentric Microlens, CLCC Package, Sealed Clear
Cover Glass with AR Coating (Both Sides), Engineering Grade.
Gen2 Color (Bayer RGB), Telecentric Microlens, PGA Package, Sealed Clear
Cover Glass (No Coatings), Grade 2.
Gen2 Color (Bayer RGB), Telecentric Microlens, PGA Package, Sealed Clear
Cover Glass (No Coatings), Engineering Grade.
Gen2 Color (Bayer RGB), Telecentric Microlens, PGA Package, Sealed Clear
Cover Glass (No Coatings), Grade 2, Packed in Trays.
KAI−02050−FBA
Serial Number
V
AB
= xx.x
KAI−02050−FBA
Serial Number
KAI−02050−ABA
Serial Number
Marking Code
KAI−02050−AAA
Serial Number
See the ON Semiconductor
Device Nomenclature
document (TND310/D) for a full description of the naming convention
used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.
www.onsemi.com
2
KAI−02050
Not Recommended for New Designs
Table 3. ORDERING INFORMATION
−
NOT RECOMMENDED FOR NEW DESIGNS
Part Number
KAI−02050−CBA−JD−BA
KAI−02050−CBA−JD−AE
KAI−02050−CBA−FD−BA
KAI−02050−CBA−FD−AE
KAI−02050−CBA−JB−B2
KAI−02050−CBA−JB−AE
KAI−02050−CBA−JB−B2−T
Description
Gen1 Color (Bayer RGB), Telecentric Microlens, PGA Package, Sealed Clear
Cover Glass with AR Coating (Both Sides), Standard Grade.
Gen1 Color (Bayer RGB), Telecentric Microlens, PGA Package, Sealed Clear
Cover Glass with AR Coating (Both Sides), Engineering Grade.
Gen1 Color (Bayer RGB), Telecentric Microlens, CLCC Package, Sealed Clear
Cover Glass with AR Coating (Both Sides), Standard Grade.
Gen1 Color (Bayer RGB), Telecentric Microlens, CLCC Package, Sealed Clear
Cover Glass with AR Coating (Both Sides), Engineering Grade.
Gen1 Color (Bayer RGB), Telecentric Microlens, PGA Package, Sealed Clear
Cover Glass (No Coatings), Grade 2.
Gen1 Color (Bayer RGB), Telecentric Microlens, PGA Package, Sealed Clear
Cover Glass (No Coatings), Engineering Grade.
Gen1 Color (Bayer RGB), Telecentric Microlens, PGA Package, Sealed Clear
Cover Glass (No Coatings), Grade 2, Packed in Trays.
KAI−02050−CBA
Serial Number
V
AB
= xx.x
KAI−02050−CBA
Serial Number
Marking Code
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3
KAI−02050
DEVICE DESCRIPTION
Architecture
H2Bc
H2Sc
H1Bc
H1Sc
H2Bd
H2Sd
H1Bd
H1Sd
SUB
GND
OGc
H2SLc
V1T
V2T
V3T
V4T
ESD
V1B
V2B
V3B
V4B
1 10 22 20
8
GND
OGa
H2SLa
Dark Reference Pixels
There are 12 dark reference rows at the top and 12 dark
rows at the bottom of the image sensor. The dark rows are not
entirely dark and so should not be used for a dark reference
level. Use the 22 dark columns on the left or right side of the
image sensor as a dark reference.
Under normal circumstances use only the center 20
columns of the 22 column dark reference due to potential
light leakage.
Dummy Pixels
Within each horizontal shift register there are 11 leading
additional shift phases. These pixels are designated as
dummy pixels and should not be used to determine a dark
reference level.
In addition, there is one dummy row of pixels at the top
and bottom of the image.
Active Buffer Pixels
20 unshielded pixels adjacent to any leading or trailing
dark reference regions are classified as active buffer pixels.
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
RDa
Ra
VDDa
VOUTa
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
1 Dummy
12
20
22 20
RDc
Rc
VDDc
VOUTc
1 10 22 20
8
800
800
20 22 10 1
8
RDd
Rd
VDDd
VOUTd
GND
OGd
H2SLd
V1T
V2T
V3T
V4T
DevID
1600 (H) x 1200 (V)
5.5
mm
x 5.5
mm
Pixels
20 22
ESD
BG
G R
20 Buffer
12 Dark
1 Dummy
V1B
V2B
V3B
V4B
(Last VCCD Phase = V1
→
H1S)
800
800
20 22 10 1
8
RDb
Rb
VDDb
VOUTb
GND
OGb
H2SLb
H2Bb
H2Sb
H1Bb
H1Sb
H2Ba
H2Sa
H1Ba
H1Sa
Figure 2. Block Diagram
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4
SUB
These pixels are light sensitive but are not tested for defects
and non-uniformities.
Image Acquisition
An electronic representation of an image is formed when
incident photons falling on the sensor plane create
electron-hole pairs within the individual silicon
photodiodes. These photoelectrons are collected locally by
the formation of potential wells at each photosite. Below
photodiode saturation, the number of photoelectrons
collected at each pixel is linearly dependent upon light level
and exposure time and non-linearly dependent on
wavelength. When the photodiodes charge capacity is
reached, excess electrons are discharged into the substrate to
prevent blooming.
ESD Protection
Adherence to the power-up and power-down sequence is
critical. Failure to follow the proper power-up and
power-down sequences may cause damage to the sensor. See
Power-Up and Power-Down Sequence section.
KAI−02050
Physical Description
PGA Pin Description and Device Orientation
67
V3T
65
V1T
63
VDDc
61
GND
59
Rc
57
H2SLc
55
H1Bc
53
H2Sc
51
N/C
49
H2Sd
47
H1Bd
45
H2SLd
43
Rd
41
GND
39
VDDd
37
V1T
35
V3T
68
ESD
66
V4T
64
V2T
62
VOUTc
60
RDc
58
OGc
56
H2Bc
54
H1Sc
52
SUB
50
H1Sd
48
H2Bd
46
OGd
44
RDd
42
VOUTd
40
V2T
38
V4T
36
DevID
Pixel (1, 1)
4
V4B
6
V2B
8
VOUTa
10
RDa
12
OGa
14
H2Ba
16
H1Sa
18
SUB
20
H1Sb
22
H2Bb
24
OGb
26
RDb
28
VOUTb
30
V2B
32
V4B
34
ESD
1
V3B
3
V1B
5
VDDa
7
GND
9
Ra
11
H2SLa
13
H1Ba
15
H2Sa
17
N/C
19
H2Sb
21
H1Bb
23
H2SLb
25
Rb
27
GND
29
VDDb
31
V1B
33
V3B
Figure 3. PGA Package Pin Designations
−
Top View
Table 4. PGA PACKAGE PIN DESCRIPTION
Pin
1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Name
V3B
V1B
V4B
VDDa
V2B
GND
VOUTa
Ra
RDa
H2SLa
OGa
H1Ba
H2Ba
H2Sa
H1Sa
N/C
SUB
H2Sb
H1Sb
H1Bb
H2Bb
H2SLb
OGb
Vertical CCD Clock, Phase 3, Bottom
Vertical CCD Clock, Phase 1, Bottom
Vertical CCD Clock, Phase 4, Bottom
Output Amplifier Supply, Quadrant a
Vertical CCD Clock, Phase 2, Bottom
Ground
Video Output, Quadrant a
Reset Gate, Quadrant a
Reset Drain, Quadrant a
Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant a
Output Gate, Quadrant a
Horizontal CCD Clock, Phase 1, Barrier, Quadrant a
Horizontal CCD Clock, Phase 2, Barrier, Quadrant a
Horizontal CCD Clock, Phase 2, Storage, Quadrant a
Horizontal CCD Clock, Phase 1, Storage, Quadrant a
No Connect
Substrate
Horizontal CCD Clock, Phase 2, Storage, Quadrant b
Horizontal CCD Clock, Phase 1, Storage, Quadrant b
Horizontal CCD Clock, Phase 1, Barrier, Quadrant b
Horizontal CCD Clock, Phase 2, Barrier, Quadrant b
Horizontal CCD Clock, Phase 1, Storage, Last Phase, Quadrant b
Output Gate, Quadrant b
Description
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5
FPGA/CPLD
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