82566 Gigabit Platform LAN Connect
Networking Silicon
Datasheet
Product Features
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IEEE 802.3ab compliant
— Robust operation over the installed base
of Category-5 (Cat-5) twisted pair
cabling
Robust end to end connections over various
cable lengths
Full duplex at 10, 100, or 1000 Mbps and
half duplex at 10 or 100 Mbps.
IEEE 802.3ab Auto-negotiation with Next
Page support
— Automatic link configuration including
speed, duplex, and flow control
10/100 downshift
— Automatic link speed adjustment with
poor quality cable
Automatic MDI crossover
— Helps to correct for infrastructure issues
Advanced Cable Diagnostics
— Improved end-user troubleshooting
Footprint compatible with 82562V devices
for a single-board dual design (Gigabit and
10/100)
LCI interface for a very low power 10/100
link
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Gigabit LAN Connect Interface
— Low pin count, high speed interface
with special low power idle modes
— Allows PHY placement proximity to I/O
back panel.
3 LED outputs
— Link and Activity indications (10, 100,
and 1000 Mbps)
Clock supplied to MAC
— Cost optimized design
Full chip power down
— Support for lowest power state
81-pin, 1.0 mm pitch, 10 mm x 10 mm
FCMMAP (BGA) Package
— Smaller footprint and lower power
dissipation compared to multi-chip
MAC and PHY solutions. Footprint
compatible with the Intel
®
82562V
Platform LAN Connect device
Integrated voltage regulator and power
supply control, which can be powered from
a single 3.3V DC rail
Operating temperatures: 0° C to 70° C and
0° C to 55° C (with internal regulator) –
heat sink or forced airflow not required
— Simple Thermal Design
Power Consumption less than 1.16 Watts
(silicon power)
317436-003
Revision 2.4
Revision History
Date
December 2007
Revision
2.4
•
•
August 2007
May 2007
2.3
2.2
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August 2006
2.1
•
•
Comments
Removed 802.3 SerDes reference in section 1.0.
Updated Section 1.2. Added reference document “Implementing the
Intel® Auto Connect Battery Saver (ACBS) With the Intel® 82566”.
Added ICH9 information.
Added new power consumption table for the 82566 DC/DM.
Change ballout row “I” to “J”. Changed all “I” pinout designations to
“J”.
Updated crystal specifications.
Replaced Figure 4.
Removed Vcase parameter from Table 9.
Removed section 3.4 “Thermal Diode (TD)”. This information can now
be found in the
82566 Gigabit Platform LAN Connect Thermal Design
Considerations
Application Note.
Revised section 4.2 title.
Revised Table 10 (removed operating temperature range parameter
and related notes).
Changed all “J” pinout designations to “I” to match Figure 10 “Visual
Pin Assignments”.
Added note to Table 16.
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June 2006
March 2006
2.0
1.5
Initial public release.
•
Initial Intel Confidential release.
Legal Notice
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel product(s) described in this document may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:
Intel Corporation
P.O. Box 5937
Denver, CO 80217-9808
or call in North America 1-800-548-4725, Europe 44-0-1793-431-155, France 44-0-1793-421-777, Germany 44-0-1793-421-333, other Countries 708-
296-9333.
Intel® is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.
Copyright © 2007, Intel Corporation.
* Third-party brands and names are the property of their respective owners.
ii
82566 Gigabit Platform LAN Connect Networking Silicon Datasheet
Contents
1.0
Introduction......................................................................................................................... 1
1.1
1.2
1.3
2.0
2.1
2.2
2.3
2.4
2.5
Document Scope................................................................................................... 2
Reference Documents...........................................................................................2
Product Codes....................................................................................................... 2
Signal Type Definitions.......................................................................................... 3
Gigabit LAN Connect Interface (GLCI) Pins.......................................................... 3
LAN Connect Interface (LCI) Pins ......................................................................... 4
Miscellaneous Pins................................................................................................ 4
PHY Pins ............................................................................................................... 5
2.5.1 LEDs......................................................................................................... 5
2.5.2 Analog Pins .............................................................................................. 5
2.5.3 Testability Pins ......................................................................................... 6
Power Supply Pins ................................................................................................ 6
Absolute Maximum Ratings................................................................................... 9
Recommended Operating Conditions ................................................................... 9
DC and AC Characteristics .................................................................................10
LED/TEST/JTAG I/F DC Specifications ..............................................................10
Power Supply Connections .................................................................................11
3.5.1 External Voltage Regulator (EVR) Power Delivery ................................11
3.5.2 Internal Voltage Regulator (IVR) Power Delivery ...................................13
3.5.3 Crystal ....................................................................................................17
Power Consumption ............................................................................................19
Package Information ...........................................................................................21
Thermal ...............................................................................................................24
Internal Pull-Up Resistors....................................................................................24
Pull-Up and Pull-Down Current ...........................................................................25
Visual Pin Assignments.......................................................................................26
Signal Descriptions............................................................................................................. 3
2.6
3.0
3.1
3.2
3.3
3.4
3.5
Voltage, Temperature, and Timing Specifications.............................................................. 9
3.6
4.0
4.1
4.2
4.3
4.4
4.5
Package and Pinout Information ......................................................................................21
Figures
1
2
3
4
5
6
7
8
9
10
82566 Block Diagram ............................................................................................ 1
External LVR Power-up Sequence......................................................................13
Internal LVR Power-up Sequence.......................................................................14
Crystal Connectivity to the 82566........................................................................18
Mechanical Drawing (1 of 4)................................................................................21
Mechanical Drawing (2 of 4)................................................................................22
Mechanical Drawing (3 of 4)................................................................................23
Mechanical Drawing (4 of 4)................................................................................24
Vpad versus Ipad ................................................................................................25
82566 Pinout (Top View - Balls Down)................................................................26
iii
82566 Gigabit Platform LAN Connect Networking Silicon Datasheet
Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Product Ordering Codes ....................................................................................... 2
GLCI Pins.............................................................................................................. 3
LCI Pins................................................................................................................. 4
Miscellaneous Pins ............................................................................................... 4
LED Pins ............................................................................................................... 5
Analog Pins ........................................................................................................... 5
Testability Pins ...................................................................................................... 6
Power Supply Pins ................................................................................................ 6
Absolute Maximum Ratings ................................................................................. 9
Recommended Operating Conditions ................................................................... 9
Preliminary DC and AC Characteristics .............................................................. 10
Preliminary LED/TEST/JTAG I/F DC Specifications ........................................... 10
3.3V DC External Power Supply Parameters...................................................... 11
1.8V DC External Power Supply Parameters...................................................... 11
1.0V DC External Power Supply Parameters...................................................... 12
3.3V DC External Power Supply Parameters..................................................... 13
1.8V DC Internal LVR Specification .................................................................... 15
1.0V DC Internal LVR Specification .................................................................... 15
PNP Specification for 1.8V DC LVR.................................................................... 16
PNP Specification for 1.0V DC LVR.................................................................... 17
Crystal Specifications.......................................................................................... 17
Power Consumption (82566MC/MM) .................................................................. 19
Power Consumption (82566DC/DM)................................................................... 20
Internal Pull-Up Resistors ................................................................................... 24
iv
82566 Gigabit Platform LAN Connect Networking Silicon Datasheet
1.0
Introduction
The 82566 is a single port Gigabit Ethernet Physical Layer Transceiver (PHY) that connects to its
MAC through a dedicated interconnect. The 82566 is based on Intel's Gigabit PHY technology, and
supports operation at data rates of 10/100/1000 Mbps. The physical layer circuitry provides a
standard IEEE 802.3 Ethernet interface for 10BASE-T, 100BASE-TX, and 1000BASE-T
applications (802.3, 802.3u, and 802.3ab).
This device operates with the ICH8/ICH9 chipset that incorporates and integrates the media access
controller (MAC), which is referred to as the ICH8/ICH9 LAN.
The 82566 is packaged in a small footprint flip chip molded matrix array package (FCMMAP)
with 81 balls in a 9 x 9 array. The package size is 10 mm x 10 mm with a pitch of 1.0 mm, making
it attractive for small form-factor platforms.
The device interfaces with its MAC through two interfaces: Gigabit LAN Connect Interface
(GLCI) and LAN Connect Interface (LCI). The GLCI is a high speed proprietary serial interface.
The LCI is a low speed proprietary parallel bus. The 82566 operates using both interfaces; the
GLCI for 1000 Mbps traffic and LCI for all other traffic types.
Figure 1
identifies the major components of the 82566 architecture.
Figure 1. 82566 Block Diagram
LCI
GLCI
LCI
GLCI
Crystal
PLL
Multiplexer
LEDs
Testability
MDIO
Status & Control
Power
Power
Supply
PHY
82566
MDI
1
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