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HYMD18M645A6-K: 产品描述DDR DRAM Module, 8MX64, 0.75ns, CMOS, 67.60 X 31.75 X 1 MM, SODIMM-200; 产品类别存储存储; 文件大小233KB，共16页; 制造商SK Hynix(海力士); 官网地址http://www.hynix.com/eng/

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HYMD18M645A6-K概述

DDR DRAM Module, 8MX64, 0.75ns, CMOS, 67.60 X 31.75 X 1 MM, SODIMM-200

HYMD18M645A6-K规格参数

参数名称	属性值
是否无铅	含铅
是否Rohs认证	不符合
厂商名称	SK Hynix(海力士)
零件包装代码	MODULE
包装说明	DIMM, DIMM200,24
针数	200
Reach Compliance Code	compliant
ECCN代码	EAR99
访问模式	SINGLE BANK PAGE BURST
最长访问时间	0.75 ns
其他特性	AUTO/SELF REFRESH
最大时钟频率 (fCLK)	133 MHz
I/O 类型	COMMON
JESD-30 代码	R-XDMA-N200
内存密度	536870912 bit
内存集成电路类型	DDR DRAM MODULE
内存宽度	64
功能数量	1
端口数量	1
端子数量	200
字数	8388608 words
字数代码	8000000
工作模式	SYNCHRONOUS
最高工作温度	70 °C
最低工作温度
组织	8MX64
输出特性	3-STATE
封装主体材料	UNSPECIFIED
封装代码	DIMM
封装等效代码	DIMM200,24
封装形状	RECTANGULAR
封装形式	MICROELECTRONIC ASSEMBLY
峰值回流温度（摄氏度）	NOT SPECIFIED
电源	2.5 V
认证状态	Not Qualified
刷新周期	4096
自我刷新	YES
最大待机电流	0.08 A
最大压摆率	1.3 mA
最大供电电压 (Vsup)	2.7 V
最小供电电压 (Vsup)	2.3 V
标称供电电压 (Vsup)	2.5 V
表面贴装	NO
技术	CMOS
温度等级	COMMERCIAL
端子形式	NO LEAD
端子节距	0.6 mm
端子位置	DUAL
处于峰值回流温度下的最长时间	NOT SPECIFIED

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8Mx64 bits

Unbuffered DDR SDRAM SO-DIMM

HYMD18M645A(L)6-K/H/L

DESCRIPTION

Hynix HYMD18M645A(L)6-K/H/L series is unbuffered 200-pin double data rate Synchronous DRAM Small Outline Dual

In-Line Memory Modules (SO-DIMMs) which are organized as 8Mx64 high-speed memory arrays. Hynix

HYMD18M645A(L)6-K/H/L series consists of four 8Mx16 DDR SDRAM in 400mil TSOP II packages on a 200pin glass-

epoxy substrate. Hynix HYMD18M645A(L)6-K/H/L series provide a high performance 8-byte interface in 67.60mmX

31.75mm form factor of industry standard. It is suitable for easy interchange and addition.

Hynix HYMD18M645A(L)6-K/H/L series is designed for high speed of up to 133MHz and offers fully synchronous oper-

ations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are

latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising

and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All

input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and

burst lengths allow variety of device operation in high performance memory system.

Hynix HYMD18M645A(L)6-K/H/L series incorporates SPD(serial presence detect). Serial presence detect function is

implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify

DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.

FEATURES

•

64MB (8M x 64) Unbuffered DDR SO-DIMM based on

8Mx16 DDR SDRAM

JEDEC Standard 200-pin small outline dual in-line

memory module (SO-DIMM)

2.5V +/- 0.2V VDD and VDDQ Power supply

All inputs and outputs are compatible with SSTL_2

interface

Fully differential clock operations (CK & /CK) with

100MHz/125MHz/133MHz

All addresses and control inputs except Data, Data

strobes and Data masks latched on the rising edges

of the clock

•

Data(DQ), Data strobes and Write masks latched on

both rising and falling edges of the clock

Data inputs on DQS centers when write (centered

DQ)

Data strobes synchronized with output data for read

and input data for write

Programmable CAS Latency 2 / 2.5 supported

Programmable Burst Length 2 / 4 / 8 with both

sequential and interleave mode

Internal four bank operations with single pulsed RAS

Auto refresh and self refresh supported

4096 refresh cycles / 64ms

ORDERING INFORMATION

Part No.

HYMD18M645A(L)6-K

HYMD18M645A(L)6-H

HYMD18M645A(L)6-L

=2.5V

DDQ

=2.5V

Power Supply

Clock Frequency

133MHz(*DDR266A)

133MHz (*DDR266B)

100MHz (*DDR200)

Interface

Form Factor

200pin Unbuffered SO-DIMM

67.6mm x 31.75mm x 1mm

SSTL_2

* JEDEC Defined Specifications compliant

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.5/May. 02

HYMD18M645A6-K相似产品对比

	HYMD18M645A6-K	HYMD18M645A6-L	HYMD18M645A6-H	HYMD18M645AL6-K	HYMD18M645AL6-H	HYMD18M645AL6-L
描述	DDR DRAM Module, 8MX64, 0.75ns, CMOS, 67.60 X 31.75 X 1 MM, SODIMM-200	DDR DRAM Module, 8MX64, 0.8ns, CMOS, 67.60 X 31.75 X 1 MM, SODIMM-200	DDR DRAM Module, 8MX64, 0.75ns, CMOS, 67.60 X 31.75 X 1 MM, SODIMM-200	DDR DRAM Module, 8MX64, 0.75ns, CMOS, 67.60 X 31.75 X 1 MM, SODIMM-200	DDR DRAM Module, 8MX64, 0.75ns, CMOS, 67.60 X 31.75 X 1 MM, SODIMM-200	DDR DRAM Module, 8MX64, 0.8ns, CMOS, 67.60 X 31.75 X 1 MM, SODIMM-200
厂商名称	SK Hynix(海力士)	SK Hynix(海力士)	SK Hynix(海力士)	SK Hynix(海力士)	SK Hynix(海力士)	SK Hynix(海力士)
零件包装代码	MODULE	MODULE	MODULE	MODULE	MODULE	MODULE
包装说明	DIMM, DIMM200,24	DIMM, DIMM200,24	DIMM, DIMM200,24	DIMM, DIMM200,24	DIMM, DIMM200,24	DIMM, DIMM200,24
针数	200	200	200	200	200	200
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant
ECCN代码	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
访问模式	SINGLE BANK PAGE BURST	SINGLE BANK PAGE BURST	SINGLE BANK PAGE BURST	SINGLE BANK PAGE BURST	SINGLE BANK PAGE BURST	SINGLE BANK PAGE BURST
最长访问时间	0.75 ns	0.8 ns	0.75 ns	0.75 ns	0.75 ns	0.8 ns
其他特性	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
最大时钟频率 (fCLK)	133 MHz	100 MHz	133 MHz	133 MHz	133 MHz	100 MHz
I/O 类型	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
JESD-30 代码	R-XDMA-N200	R-XDMA-N200	R-XDMA-N200	R-XDMA-N200	R-XDMA-N200	R-XDMA-N200
内存密度	536870912 bit	536870912 bit	536870912 bit	536870912 bit	536870912 bit	536870912 bit
内存集成电路类型	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE
内存宽度	64	64	64	64	64	64
功能数量	1	1	1	1	1	1
端口数量	1	1	1	1	1	1
端子数量	200	200	200	200	200	200
字数	8388608 words	8388608 words	8388608 words	8388608 words	8388608 words	8388608 words
字数代码	8000000	8000000	8000000	8000000	8000000	8000000
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
组织	8MX64	8MX64	8MX64	8MX64	8MX64	8MX64
输出特性	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
封装主体材料	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
封装代码	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM
封装等效代码	DIMM200,24	DIMM200,24	DIMM200,24	DIMM200,24	DIMM200,24	DIMM200,24
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY
电源	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
刷新周期	4096	4096	4096	4096	4096	4096
自我刷新	YES	YES	YES	YES	YES	YES
最大待机电流	0.08 A	0.08 A	0.08 A	0.08 A	0.08 A	0.08 A
最大压摆率	1.3 mA	1.2 mA	1.3 mA	1.3 mA	1.3 mA	1.2 mA
最大供电电压 (Vsup)	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V
最小供电电压 (Vsup)	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V
标称供电电压 (Vsup)	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V
表面贴装	NO	NO	NO	NO	NO	NO
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
端子形式	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD
端子节距	0.6 mm	0.6 mm	0.6 mm	0.6 mm	0.6 mm	0.6 mm
端子位置	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL

HYMD18M645A6-K

HYMD18M645A6-K概述

HYMD18M645A6-K规格参数

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