2 Mbit / 4 Mbit SPI Serial Flash
SST25LF020A / SST25LF040A
SST25LF020A / 040A2Mb / 4Mb Serial Peripheral Interface (SPI) flash memory
Preliminary Specifications
FEATURES:
• Single 3.0-3.6V Read and Write Operations
• Serial Interface Architecture
– SPI Compatible: Mode 0 and Mode 3
• 33 MHz Max Clock Frequency
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption:
– Active Read Current: 7 mA (typical)
– Standby Current: 8 µA (typical)
• Flexible Erase Capability
– Uniform 4 KByte sectors
– Uniform 32 KByte overlay blocks
• Fast Erase and Byte-Program:
– Chip-Erase Time: 70 ms (typical)
– Sector- or Block-Erase Time: 18 ms (typical)
– Byte-Program Time: 14 µs (typical)
• Auto Address Increment (AAI) Programming
– Decrease total chip programming time over
Byte-Program operations
• End-of-Write Detection
– Software Status
• Hold Pin (HOLD#)
– Suspends a serial sequence to the memory
without deselecting the device
• Write Protection (WP#)
– Enables/Disables the Lock-Down function of the
status register
• Software Write Protection
– Write protection through Block-Protection bits in
status register
• Temperature Range
– Commercial: 0°C to +70°C
– Industrial: -40°C to +85°C
– Extended: -20°C to +85°C
• Packages Available
– 8-lead SOIC 150 mil body width
for SST25LF020A
– 8-lead SOIC 200 mil body width
for SST25LF040A
– 8-contact WSON (5mm x 6mm)
PRODUCT DESCRIPTION
SST’s serial flash family features a four-wire, SPI-com-
patible interface that allows for a low pin-count package
occupying less board space and ultimately lowering total
system costs. SST25LF020A/040A SPI serial flash
memories are manufactured with SST’s proprietary, high
performance CMOS SuperFlash technology. The split-
gate cell design and thick-oxide tunneling injector attain
better reliability and manufacturability compared with
alternate approaches.
The SST25LF020A/040A devices significantly improve
performance, while lowering power consumption. The
total energy consumed is a function of the applied volt-
age, current, and time of application. Since for any given
voltage range, the SuperFlash technology uses less cur-
rent to program and has a shorter erase time, the total
energy consumed during any Erase or Program operation
is less than alternative flash memory technologies. The
SST25LF020A/040A devices operate with a single 3.0-
3.6V power supply.
The SST25LF020A devices are offered in an 8-lead SOIC
150 mil body width (SA) package. The SST25LF040A
devices are offered in an 8-lead SOIC 200 mil body width
(S2A) package. All densities are offered in the 8-contact
WSON package. See Figure 1 for the pin assignments.
©2004 Silicon Storage Technology, Inc.
S71242-03-000
6/04
1
The SST logo and SuperFlash are registered Trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
2 Mbit / 4 Mbit SPI Serial Flash
SST25LF020A / SST25LF040A
Preliminary Specifications
F
UNCTIONAL
B
LOCK
D
IAGRAM
Address
Buffers
and
Latches
X - Decoder
SuperFlash
Memory
Y - Decoder
Control Logic
I/O Buffers
and
Data Latches
Serial Interface
1242 B1.0
CE#
SCK
SI
SO
WP#
HOLD#
©2004 Silicon Storage Technology, Inc.
S71242-03-000
6/04
2
2 Mbit / 4 Mbit SPI Serial Flash
SST25LF020A / SST25LF040A
Preliminary Specifications
PIN DESCRIPTION
CE#
SO
WP#
VSS
1
2
8
7
VDD
HOLD#
SCK
SI
CE#
SO
WP#
VSS
1
8
VDD
HOLD#
SCK
SI
2
7
Top View
3
4
6
5
1242 08-soic P1.0
3
Top View
6
4
5
1242 08-wson P2.0
8-
LEAD
SOIC
FIGURE 1: P
IN
A
SSIGNMENTS
TABLE 1: P
IN
D
ESCRIPTION
Symbol Pin Name
SCK
Serial Clock
Functions
8-
CONTACT
WSON
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock input, while output
data is shifted out on the falling edge of the clock input.
To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
The device is enabled by a high to low transition on CE#. CE# must remain low for the duration of
any command sequence.
The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
To temporarily stop serial communication with SPI flash memory without resetting the device.
To provide power supply (3.0-3.6V).
T1.0 1242
SI
SO
CE#
WP#
HOLD#
V
DD
V
SS
Serial Data
Input
Serial Data
Output
Chip Enable
Write Protect
Hold
Power Supply
Ground
©2004 Silicon Storage Technology, Inc.
S71242-03-000
6/04
3
2 Mbit / 4 Mbit SPI Serial Flash
SST25LF020A / SST25LF040A
Preliminary Specifications
PRODUCT IDENTIFICATION
TABLE 2: P
RODUCT
I
DENTIFICATION
Address
Manufacturer’s ID
Device ID
SST25LF020A
SST25LF040A
00001H
00001H
43H
44H
T2.0 1242
DEVICE OPERATION
The SST25LF020A/040A is accessed through the SPI
(Serial Peripheral Interface) bus compatible protocol. The
SPI bus consist of four control lines; Chip Enable (CE#) is
used to select the device, and data is accessed through the
Serial Data Input (SI), Serial Data Output (SO), and Serial
Clock (SCK).
The SST25LF020A/040A supports both Mode 0 (0,0) and
Mode 3 (1,1) of SPI bus operations. The difference
between the two modes, as shown in Figure 2, is the state
of the SCK signal when the bus master is in Stand-by
mode and no data is being transferred. The SCK signal is
low for Mode 0 and SCK signal is high for Mode 3. For both
modes, the Serial Data In (SI) is sampled at the rising edge
of the SCK clock signal and the Serial Data Output (SO) is
driven after the falling edge of the SCK clock signal.
Data
BFH
00000H
MEMORY ORGANIZATION
The SST25LF020A/040A SuperFlash memory array is
organized in 4 KByte sectors with 32 KByte overlay blocks.
CE#
MODE 3
MODE 3
MODE 0
SCK
SI
SO
MODE 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
DON'T CARE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
1242 F02.0
HIGH IMPEDANCE
FIGURE 2: SPI P
ROTOCOL
©2004 Silicon Storage Technology, Inc.
S71242-03-000
6/04
4
2 Mbit / 4 Mbit SPI Serial Flash
SST25LF020A / SST25LF040A
Preliminary Specifications
Hold Operation
HOLD# pin is used to pause a serial sequence underway
with the SPI flash memory without resetting the clocking
sequence. To activate the HOLD# mode, CE# must be in
active low state. The HOLD# mode begins when the SCK
active low state coincides with the falling edge of the
HOLD# signal. The HOLD mode ends when the HOLD#
signal’s rising edge coincides with the SCK active low state.
If the falling edge of the HOLD# signal does not coincide
with the SCK active low state, then the device enters Hold
mode when the SCK next reaches the active low state.
Similarly, if the rising edge of the HOLD# signal does not
coincide with the SCK active low state, then the device
exits in Hold mode when the SCK next reaches the active
low state. See Figure 3 for Hold Condition waveform.
Once the device enters Hold mode, SO will be in high-
impedance state while SI and SCK can be V
IL
or V
IH
.
If CE# is driven active high during a Hold condition, it resets
the internal logic of the device. As long as HOLD# signal is
low, the memory remains in the Hold condition. To resume
communication with the device, HOLD# must be driven
active high, and CE# must be driven active low. See Figure
18 for Hold timing.
SCK
HOLD#
Active
Hold
Active
Hold
Active
1242 F03.0
FIGURE 3: H
OLD
C
ONDITION
W
AVEFORM
Write Protection
SST25LF020A/040A provides software Write protection.
The Write Protect pin (WP#) enables or disables the lock-
down function of the status register. The Block-Protection
bits (BP1, BP0, and BPL) in the status register provide
Write protection to the memory array and the status regis-
ter. See Table 5 for Block-Protection description.
Write Protect Pin (WP#)
The Write Protect (WP#) pin enables the lock-down func-
tion of the BPL bit (bit 7) in the status register. When WP#
is driven low, the execution of the Write-Status-Register
(WRSR) instruction is determined by the value of the BPL
bit (see Table 3). When WP# is high, the lock-down func-
tion of the BPL bit is disabled.
TABLE 3: C
ONDITIONS TO EXECUTE
W
RITE
-S
TATUS
-
R
EGISTER
(WRSR) I
NSTRUCTION
WP#
L
L
H
BPL
1
0
X
Execute WRSR Instruction
Not Allowed
Allowed
Allowed
T3.0 1242
©2004 Silicon Storage Technology, Inc.
S71242-03-000
6/04
5
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