LH79520
Preliminary data sheet
FEATURES
• Highly Integrated System-on-Chip
• High Performance (77.4144 MHz CPU Speed)
• ARM720T™ RISC Core
– 32-bit ARM7TDMI™ RISC Core
– 8 kB Cache
– MMU (Windows CE™ Enabled)
– Write Buffer
• 32 kB On-Chip SRAM
• Flexible, Programmable Memory Interface
– SDRAM Interface
– 15-bit External Address Bus
– 32-bit External Data Bus
– Two Segments (128 MB each)
– SRAM/Flash/ROM Interface
– 26-bit External Address Bus
– 32-bit External Data Bus
– Seven Segments (64 MB Each)
• Multi-stream DMA Controller
– Four 32-bit Burst-based Data Streams
• Clock and Power Management
– 32.768 kHz Oscillator for Real Time Clock
– 14.7456 MHz Oscillator and On-chip PLL for
CPU and Bus Clocks
– Active, Standby, Sleep and Stop Power Modes
– Externally-supplied Clock Options
• Low Power Modes
– Active Mode: 55 mA (MAX.)
– Standby Mode: 35 mA (MAX.)
– Sleep Mode: 5.5 mA (MAX.)
– Stop Mode 2: 18
µA
• Watchdog Timer
• Vectored Interrupt Controller
– 16 Standard and 16 Vectored IRQ Interrupts
– Hardware Interrupt Priority
– Software Interrupts
– FIQ Fast Interrupts
• Three UARTs
– 16-byte FIFOs for Rx and Tx
– IrDA SIR Support
– Supports Data Rates Up to 460.8 kb/s
• Two 16-bit Pulse Width Modulators
• Two Dual Channel Timer Modules
• Real Time Clock
– 32-bit Up-counter with Programmable Load
– Programmable 32-bit Match Compare Register
System-on-Chip
• 64 Programmable General Purpose I/O Signals
– Multiplexed with Peripheral I/O Signals
• Programmable Color LCD Controller
– Up to 800 × 600 Resolution
– Supports STN, Color STN, AD-TFT, TFT
– Supports 15 Shades of Gray
– TFT: Supports 64 k Direct Colors or 256 Colors
selected from a Palette of 64,000 Colors
– Color STN: Supports 3,375 Direct Colors or 256
Colors Selected from a Palette of 3,375 Colors
• Synchronous Serial Port
– Supports Data Rates Up to 1.8452 Mb/s
– Compatible with Common Interface Schemes
– Motorola SPI™
– National Semiconductor MICROWIRE™
– Texas Instruments SSI
• JTAG Debug Interface and Boundary Scan
• 5 V Tolerant Digital I/O
– XTALIN and XTAL32IN inputs are 1.8 V ± 10 %
DESCRIPTION
The LH79520, powered by an ARM720T, is a com-
plete System-on-Chip with a high level of integration to
satisfy a wide range of requirements and expectations.
The LH79520 combines a 32-bit ARM720T RISC,
Color LCD controller, Cache, Local SRAM, a number of
essential peripherals such as Direct Memory Access,
Serial and Parallel Interfaces, Infrared support, Timers,
Real Time Clock, Watchdog Timer, Pulse Width Modu-
lators, and an on-chip Phase Lock Loop. Debug is
made simple by JTAG support.
This high level of integration lowers overall system
costs, reduces development cycle time and acceler-
ates product introduction. The LH79520’s fully static
design, power management unit, low voltage operation
(1.8 V Core, 3.3 V I/O), on-chip PLL, fast interrupt
response time, on-chip cache and SRAM, powerful
instruction set, and low power RISC core provide high
performance.
To build an advanced portable device, advanced pro-
cessing capability is required. This capability must come
with increased performance in the display system and
peripherals, and yet demand less power from batteries.
The LH79520 is an integrated solution to fit these needs.
Preliminary data sheet
1
System-on-Chip
NXP Semiconductors
LH79520
SIGNAL DESCRIPTIONS
Table 2. LH79520 Signal Descriptions
PIN NO.
2-7
9-12
14-17
19-22
24-27
29-32
50-54
56-63
65-66
67-69
71-74
76-79
81-84
86-87
101
109
110
111
112
102
104
105
107
108
106
41
42
43
44
46
47
48
38
34
35
36
37
39
144
148
147
146
157
145
144
SIGNAL NAME
TYPE
DESCRIPTION
MEMORY INTERFACE (MI)
NOTES
A[25:0]
Output
Address Signals
D[31:0]
Input/Output
Data Input/Output Signals
1
SDCLK
DQM3
DQM2
DQM1
DQM0
SDCKE
nDCS1
nDCS0
nRAS
nCAS
nSDWE
nCS6
nCS5
nCS4
nCS3
nCS2
nCS1
nCS0
nOE
nBLE3
nBLE2
nBLE1
nBLE0
nWE
nWAIT
DEOT0
nDACK0
DREQ0
DEOT1
DACK1
DREQ1
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Output
Output
Input
Output
Output
Input
SDRAM Clock
Data Mask Output to SDRAMs
Data Mask Output to SDRAMs
Data Mask Output to SDRAMs
Data Mask Output to SDRAMs
SDRAM Clock Enable
SDRAM Chip Select
SDRAM Chip Select
Row Address Strobe
Column Address Strobe
SDRAM Write Enable
Static Memory Controller Chip Select
Static Memory Controller Chip Select
Static Memory Controller Chip Select
Static Memory Controller Chip Select
Static Memory Controller Chip Select
Static Memory Controller Chip Select
Static Memory Controller Chip Select
Static Memory Controller Output Enable
Static Memory Controller Byte Lane Enable / Byte Write Enable
Static Memory Controller Byte Lane Enable / Byte Write Enable
Static Memory Controller Byte Lane Enable / Byte Write Enable
Static Memory Controller Byte Lane Enable / Byte Write Enable
Static Memory Controller Write Enable
Static Memory Controller External Wait Control
DMA CONTROLLER (DMAC)
DMA 0 End of Transfer
DMA 0 Acknowledge
DMA 0 Request
DMA 1 End of Transfer
DMA 1 Acknowledge
DMA 1 Request
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1, 3
1
1
1
1
1
1, 3
Preliminary data sheet
Rev. 01
—
16 July 2007
5
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