19-2029; Rev 1; 11/10
KIT
ATION
EVALU
BLE
AVAILA
10-Bit Bus LVDS Serializers
General Description
Features
o
Standalone Serializer (vs. SERDES) Ideal for
Unidirectional Links
o
Framing Bits for Deserializer Resync Allow Hot
Insertion Without System Interruption
o
LVDS Serial Output Rated for Point-to-Point and
Bus Applications
o
Wide Reference Clock Input Range
16MHz to 40MHz (MAX9205)
40MHz to 66MHz (MAX9207)
o
Low 140ps (pk-pk) Deterministic Jitter (MAX9207)
o
Low 34mA Supply Current (MAX9205)
o
10-Bit Parallel LVCMOS/LVTTL Interface
o
Up to 660Mbps Payload Data Rate (MAX9207)
o
Programmable Active Edge on Input Latch
o
Pin-Compatible Upgrades to DS92LV1021 and
DS92LV1023
MAX9205/MAX9207
The MAX9205/MAX9207 serializers transform 10-bit-
wide parallel LVCMOS/LVTTL data into a serial high-
speed bus low-voltage differential signaling (LVDS)
data stream. The serializers typically pair with deserial-
izers like the MAX9206/MAX9208, which receive the
serial output and transform it back to 10-bit-wide paral-
lel data.
The MAX9205/MAX9207 transmit serial data at speeds
up to 400Mbps and 660Mbps, respectively, over PCB
traces or twisted-pair cables. Since the clock is recov-
ered from the serial data stream, clock-to-data and
data-to-data skew that would be present with a parallel
bus are eliminated.
The serializers require no external components and few
control signals. The input data strobe edge is selected
by TCLK_R/F.
PWRDN
is used to save power when the
devices are not in use. Upon power-up, a synchroniza-
tion mode is activated, which is controlled by two SYNC
inputs, SYNC1 and SYNC2.
The MAX9205 can lock to a 16MHz to 40MHz system
clock, while the MAX9207 can lock to a 40MHz to
66MHz system clock. The serializer output is held in
high impedance until the device is fully locked to the
local system clock, or when the device is in power-
down mode.
Both the devices operate from a single +3.3V supply,
are specified for operation from -40°C to +85°C, and
are available in 28-pin SSOP packages.
Ordering Information
PART
MAX9205EAI+
MAX9207EAI+
TEMP
RANGE
PIN-
PACKAGE
REF CLOCK
RANGE
(MHz)
16 to 40
16 to 40
40 to 66
-40°C to +85°C 28 SSOP
-40°C to +85°C 28 SSOP
Applications
Cellular Phone Base
Stations
Add Drop Muxes
Digital Cross-Connects
DSLAMs
Network Switches and
Routers
Backplane Interconnect
MAX9205EAI/V+ -40°C to +85°C 28 SSOP
+Denotes
a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive qualified part.
Pin Configuration and Functional Diagram appear at end of
data sheet.
Typical Application Circuit
PARALLEL-TO-SERIAL
OUT+
100Ω
OUT-
PCB OR
TWISTED PAIR
EN
PWRDN
MAX9205
MAX9207
MAX9206
MAX9208
PLL
IN+
100Ω
IN-
SERIAL-TO-PARALLEL
BUS
LVDS
OUTPUT LATCH
INPUT LATCH
10
IN_
TCLK_R/F
TCLK
10
OUT_
REFCLK
TIMING AND
CONTROL
CLOCK
RECOVERY
EN
LOCK
RCLK
RCLK_R/F
PLL
SYNC 1
SYNC 2
TIMING AND
CONTROL
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
10-Bit Bus LVDS Serializers
MAX9205/MAX9207
ABSOLUTE MAXIMUM RATINGS
AVCC, DVCC to GND..........................……………-0.3V to +4.0V
IN_, SYNC1, SYNC2, EN, TCLK_R/F, TCLK,
PWRDN
to GND......................................-0.3V to (V
CC
+ 0.3V)
OUT+, OUT- to GND .............................................-0.3V to +4.0V
Output Short-Circuit Duration.....................................Continuous
Continuous Power Dissipation (T
A
= +70°C)
28-Pin SSOP (derate 9.5mW/°C above +70°C) ..........762mW
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature ......................................................+150°C
Operating Temperature Range ...........................-40°C to +85°C
ESD Protection (Human Body Model, OUT+, OUT-) ...........±8kV
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
AVCC
= V
DVCC
= +3.0V to +3.6V, R
L
= 27Ω ±1% or 50Ω ±1%, C
L
= 10pF, T
A
= -40°C to +85°C. Typical values are at V
AVCC
=
V
DVCC
= +3.3V and T
A
= +25°C, unless otherwise noted.) (Notes 1, 2, 3)
PARAMETER
High-Level Input Voltage
Low-Level Input Voltage
SYMBOL
V
IH
V
IL
V
IN_
= 0V or V
_VCC
R
L
= 27Ω
R
L
= 50Ω
CONDITIONS
MIN
2.0
GND
-20
200
250
286
460
1
0.9
1.15
3
-13
-10
-10
23
34
32
45
TYP
MAX
V
CC
0.8
+20
400
600
35
1.3
35
-15
+10
+10
35
45
50
60
8
mA
mA
UNITS
V
V
µA
mV
mV
mV
V
mV
mA
µA
µA
LVCMOS/LVTLL LOGIC INPUTS (IN0 TO IN9, EN, SYNC1, SYNC2, TCLK, TCLK_R/F,
PWRDN)
Input Current
I
IN
BUS LVDS OUTPUTS (OUT+, OUT-)
Differential Output Voltage
Change in V
OD
Between
Complementary Output States
Output Offset Voltage
Change in V
OS
Between
Complementary Output States
Output Short-Circuit Current
Output High-Impedance Current
Power-Off Output Current
POWER SUPPLY
V
OD
ΔV
OD
V
OS
ΔV
OS
I
OS
I
OZ
I
OX
Figure 1
Figure 1
Figure 1
Figure 1
V
OUT+
or V
OUT-
= 0V,
IN0 to IN9 =
PWRDN
= EN = high
V
PWRDN
or V
EN
= 0.8V,
V
OUT+
or V
OUT-
= 0V or V
_VCC
V
_VCC
= 0V, V
OUT+
or V
OUT-
= 0V or 3.6V
16MHz
40MHz
40MHz
66MHz
Supply Current
I
CC
R
L
= 27_ or 50_
worst-case pattern
(Figures 2, 4)
PWRDN
= low
MAX9205
MAX9207
Power-Down Supply Current
I
CCX
2
_______________________________________________________________________________________
10-Bit Bus LVDS Serializers
AC ELECTRICAL CHARACTERISTICS
(V
AVCC
= V
DVCC
= +3.0V to +3.6V, R
L
= 27Ω ±1% or 50Ω ±1%, C
L
= 10pF, T
A
= -40°C to +85°C. Typical values are at V
AVCC
=
V
DVCC
= +3.3V and T
A
= +25°C, unless otherwise noted.) (Notes 2, 4)
PARAMETER
SYMBOL
CONDITIONS
MAX9205
MAX9207
MAX9205
MAX9207
Figure 3
MIN
16
40
-200
25
15.15
40
3
TYP
MAX
40
66
200
62.5
25
60
6
150
UNITS
MHz
MHz
ppm
ns
%
ns
ps
(RMS)
MAX9205/MAX9207
TRANSMIT CLOCK (TCLK) TIMING REQUIREMENTS
TCLK Center Frequency
TCLK Frequency Variation
TCLK Period
TCLK Duty Cycle
TCLK Input Transition Time
TCLK Input Jitter
SWITCHING CHARACTERISTICS
Low-to-High Transition Time
High-to-Low Transition Time
IN_ Setup to TCLK
IN_ Hold from TCLK
OUTPUT High State to High-
Impedance Delay
OUTPUT Low State to High-
Impedance Delay
OUTPUT High Impedance to
High-State Delay
OUTPUT High Impedance to
Low-State Delay
SYNC Pulse Width
PLL Lock Time
Bus LVDS Bit Width
Serializer Delay
t
LHT
t
HLT
t
S
t
H
t
HZ
t
LZ
t
ZH
t
ZL
t
SPW
t
PL
t
BIT
t
SD
Figure 8
t
TCP
/ 6
Figure 7
Figure 4
Figure 4
Figure 5
Figure 5
Figures 6, 7
Figures 6, 7
Figures 6, 7
Figures 6, 7
6 x t
TCP
2048 x
t
TCP
t
TCP
/12
(t
TCP
/6)
+5
2049 x
t
TCP
R
L
= 27
R
L
= 50
R
L
= 27
R
L
= 50
150
150
150
150
1
3
4.5
4.5
4.5
4.5
10
10
10
10
300
350
300
350
400
500
400
500
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
f
TCCF
TCFV
t
TCP
TCDC
t
CLKT
t
JIT
_______________________________________________________________________________________
3
10-Bit Bus LVDS Serializers
MAX9205/MAX9207
AC ELECTRICAL CHARACTERISTICS (continued)
(V
AVCC
= V
DVCC
= +3.0V to +3.6V, R
L
= 27Ω ±1% or 50Ω ±1%, C
L
= 10pF, T
A
= -40°C to +85°C. Typical values are at V
AVCC
=
V
DVCC
= +3.3V and T
A
= +25°C, unless otherwise noted.) (Notes 2, 4)
PARAMETER
SYMBOL
MAX9205
Deterministic Jitter (Figure 9)
t
DJIT
MAX9207
MAX9205
Random Jitter (Figure 10)
t
RJIT
MAX9207
CONDITIONS
16MHz
40MHz
40MHz
66MHz
16MHz
40MHz
40MHz
66MHz
MIN
TYP
MAX
200
140
140
140
13
9
9
6
ps
(RMS)
ps
(pk-pk)
UNITS
Note 1:
Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except V
OD
,
ΔV
OD
, and V
OS
.
Note 2:
C
L
includes scope probe and test jig capacitance.
Note 3:
Parameters 100% tested at T
A
= +25°C. Limits over operating temperature range guaranteed by design and characterization.
Note 4:
AC parameters are guaranteed by design and characterization.
Typical Operating Characteristics
(V
AVCC
= V
DVCC
= +3.3V, R
L
= 27Ω, C
L
= 10pF, T
A
= +25°C, unless otherwise noted.)
WORST-CASE PATTERN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX9205 toc01
WORST-CASE PATTERN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX9205 toc01
50
50
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
40
40
30
30
20
TCLK = 40MHz
MAX9205
20
TCLK = 40MHz
MAX9205
10
3.0
3.3
SUPPLY VOLTAGE (V)
3.6
10
3.0
3.3
SUPPLY VOLTAGE (V)
3.6
4
_______________________________________________________________________________________
10-Bit Bus LVDS Serializers
Pin Description
PIN
NAME
FUNCTION
LVCMOS/LVTTL Logic Inputs. The two SYNC pins are ORed. When at least one of the two pins
are asserted high for at least six cycles of TCLK, the serializer initiates a transmission of 1024
SYNC patterns. If held high after 1024 SYNC patterns have been transmitted, SYNC patterns
continue to be sent until the SYNC pin is asserted low. Toggling a SYNC pin after six TCLK cycles
high and before 1024 SYNC patterns have been transmitted does not affect the output of the 1024
SYNC patterns.
LVCMOS/LVTTL Data Inputs. Data is loaded into a 10-bit latch by the selected TCLK edge.
LVCMOS/LVTTL Logic Input. High selects a TCLK rising-edge data strobe. Low selects a TCLK
falling-edge data strobe.
LVCMOS/LVTTL Reference Clock Input. The MAX9205 accepts a 16MHz to 40MHz clock. The
MAX9207 accepts a 40MHz to 66MHz clock. TCLK provides a frequency reference to the PLL and
strobes parallel data into the input latch.
Digital Circuit Ground. Connect to ground plane.
Analog Circuit Power Supply (Includes PLL). Bypass AVCC to ground with a 0.1µF capacitor and a
0.001µF capacitor. Place the 0.001µF capacitor closest to AVCC.
Analog Circuit Ground. Connect to ground plane.
LVCMOS/LVTTL Logic Input. High enables serial data output. Low puts the bus LVDS output into
high impedance.
Inverting Bus LVDS Differential Output
Noninverting Bus LVDS Differential Output
LVCMOS/LVTTL Logic Input. Low puts the device into power-down mode and the output into high
impedance.
Digital Circuit Power Supply. Bypass DVCC to ground with a 0.1µF capacitor and a 0.001µF
capacitor. Place the 0.001µF capacitor closest to DVCC.
MAX9205/MAX9207
1, 2
SYNC 1,
SYNC 2
3–12
13
IN0–IN9
TCLK_R/F
14
15, 16
17, 26
18, 20,
23, 25
19
21
22
24
27, 28
TCLK
DGND
AVCC
AGND
EN
OUT-
OUT+
PWRDN
DVCC
Detailed Description
The MAX9205/MAX9207 are 10-bit serializers designed
to transmit data over balanced media that may be a
standard twisted-pair cable or PCB traces at 160Mbps
to 660Mbps. The interface may be double-terminated
point-to-point or a heavily loaded multipoint bus. The
characteristic impedance of the media and connected
devices can range from 100Ω for a point-to-point inter-
face to 54Ω for a heavily loaded multipoint bus. A dou-
ble-terminated point-to-point interface uses a
100Ω-termination resistor at each end of the interface,
resulting in a load of 50Ω. A heavily loaded multipoint
bus requires a termination as low as 54Ω at each end
of the bus, resulting in a termination load of 27Ω. The
serializer requires a deserializer such as the
MAX9206/MAX9208 for a complete data transmission
application.
A high-state start bit and a low-state stop bit, added
internally, frame the 10-bit parallel input data and
ensure a transition in the serial data stream. Therefore,
12 serial bits are transmitted for each 10-bit parallel
input. The MAX9205 accepts a 16MHz to 40MHz refer-
ence clock, producing a serial data rate of 192Mbps
(12 bits x 16MHz) to 480Mbps (12 bits x 40MHz). The
MAX9207 accepts a 40MHz to 66MHz reference clock,
producing 480Mbps to 792Mbps. However, since only
10 bits are from input data, the actual throughput is 10
times the TCLK frequency.
To transmit data, the serializers sequence through
three modes: initialization mode, synchronization mode,
and data transmission mode.
_______________________________________________________________________________________
5
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