M-986-2A1
MF Transceiver
Features
•
Direct A-Law or µ-Law PCM digital input
•
2.048 Mb/s clocking
•
Operates with standard codecs for analog interfac-
ing
•
Microprocessor read/write interface
•
Binary or 2-of-6 data formats
•
Dual-channel
•
5 volt power
Description
The M-986-2A1 dual channel MF Transceiver con-
tains all the logic necessary to transmit and receive
(North American) CCITT Region 1 multifrequency
signals on one integrated circuit (IC).
Operating with a 20.48 MHz crystal, the M-986 is
capable of providing a direct digital interface to a m-
law or A-law encoded PCM digital input. Each channel
can be connected to an analog source using a coder-
decoder (codec) as shown in the Block Diagram
below.
The M-986 is configured and controlled through an
integral coprocessor port.
Applications
•
•
•
•
•
Test equipment
Trunk adapters
Paging terminals
Traffic recorders
PBXs
Ordering Information
Part #
M-986-2A1P
M-986-2A1PL
Description
40-pin plastic DIP
44-pin PLCC
Block Diagram
DS-M986-2A1
www.clare.com
1
M-986-2A1
Absolute Maximum Ratings Over Specified
Temperature Range
Supply voltage range, V
CC
Input voltage range
Output voltage range
Ambient air temperature range
Storage temperature range
-0.3 V to 7 V
-0.3 V to 15 V
-0.3 V to 15 V
0˚ to 150˚C
-45˚C to 150˚C
Absolute Maximum Ratings are stress ratings. Stresses in
excess of these ratings can cause permanent damage to
the device. Functional operation of the device at these or
any other conditions beyond those indicated in the opera-
tional sections of this data sheet is not implied. Exposure of
the device to the absolute maximum ratings for an extend-
ed period may degrade the device and effect its reliability.
Function Description
The M-986-2A1 can be set up for various modes of
operation by writing two configuration bytes to the
coprocessor port. The format of the two configuration
bytes is shown in the Configuration Table on page 3
and the configuration options are described in the fol-
lowing paragraphs.
Configuration Options
External/Internal Codec Clock (ECLK):
If external
codec clocking is selected, an external clocking source
provides an 8 kHz transmit framing clock and an 8 kHz
receive framing clock. It also provides a serial bit clock
with a frequency that is a multiple of 8 kHz between
216 kHz and 2.496 MHz for exchange of data via the
serial ports. When internal codec clocking is selected,
the M-986-2A1 provides an 8 kHz framing clock and a
2.048 MHz serial bit clock.
2 of 6/Binary Input/Output (IOM):
When the 2-of-6
input/output is selected, the M-986-2A1 encodes the
received R1 MF tone pair into a 6-bit format, where
each bit represents one of the six possible frequencies.
A logic high level indicates the presence of a frequen-
cy. The digital input to the M-986-2A1 that selects the
transmitted R1 MF tone pair must also be coded in the
2-of-6 format.
Electrical Characteristics/Temperature Range
When binary input/output is selected, the M-986-2A1
encodes the received R1 MF tone pair into a 4 bit
binary format. The digital input to the M-986-2A1 that
selects the transmitted R1 MF tone pair must also be
coded in a 4 bit binary format.
Enable/Disable Channel (ENC): When a channel is
disabled, the receiver does not process its codec
input for R1 MF tones, and the transmitter does not
respond to transmit commands. If a transmit com-
mand is given while the channel is enabled, the “tone
off” command must be given before the channel is dis-
abled. Disabling the channel does not automatically
shut off the transmitter. When a channel is enabled,
the receiver and transmitter for that channel function
normally.
Long/Short KP Tone Detection Time (KPL): When
long KP tone detection is selected, the minimum on
time for the KP tone to be detected is 55 milliseconds.
When short KP tone detection is selected, the mini-
mum on time for the KP tone to be detected is 30 mil-
liseconds (the same as the minimum on time for the
rest of the MF tones).
Enable MF Tone Detection After Reception of KP
(KPEN): When this feature is enabled, MF tone detec-
tion is enabled after reception of the KP tone, and dis-
abled after reception of ST, ST1, ST2, or ST3 tones.
When this feature is disabled, MF tone detection is
always enabled. Select A or µ-law input/output (AMU)
for A-law encoding, this bit is set to a 1, for µ-law
encoding it is set to 0.
Typ
-
2.4
V
CC
-0.4
-
-
-
-
-
-
-
-
-
Max
50
3
-
0.3
-
-
-
-
25
15
25
10
Unit
75
-
-
0.6
20
-20
±20
±50
-
-
-
-
I
CC
V
OH
V
OL
I
OZ
I
I
C
I
C
O
Parameter
Test ConditionsMin
Supply current
f = 20.5 MHz, V
CC
= 5.5V,
T
A
= 0˚ to 70 ˚C
High-level output voltage
I
OH
= MAX
I
OH
= 20 µ A
Low-level output voltage
I
OL
= MAX
Off-state output current
V
CC
= MAX
VO = 2.4 V
VO = 0.4 V
Input current
V
I
= V
SS
to V
CC
Except CLKIN
CLKIN
Input capacitance Data bus
f = 1 MHz, all other pins 0 V
All others
Output capacitance Data bus
All others
mA
V
V
V
µA
µA
µA
µA
pF
pF
pF
pF
Rev. 3
2
www.clare.com
M-986-2A1
Configuration
Configuration Byte 1
Bit 7
0
ECLK
IOM
ENC1
KPL1
KPEN1
Bit 6
0
Bit 5
ECLK
Channels 1 & 2
Channels 1 & 2
Channel 1
Channel 1
Channel 1
Bit 4
IOM
Bit 3
ENCI
Bit 2
KPL1
Bit 1
KPEN1
Bit 0
0
1 = External codec clock; 0 = Internal codec clock
1 = Binary input/output; 0 = 2-of-6 input/output
1 = Enable channel; 0 = Disable channel
1 = 55 ms detection time for KP; 0 = 30 ms detection time for KP
1 = Enable MF tone detection after KP detection;
0 = MF tone detection always on
Configuration Byte 2
Bit 7
0
AMU
ENC2
KPL2
KPEN2
Bit 6
1
Bit 5
0
Channels 1 & 2
Channel 2
Channel 2
Channel 2
Bit 4
AMU
Bit 3
ENC2
Bit 2
KPL2
Bit 1
KPEN2
Bit 0
0
1 = A-law Encoding, 0 = m-law Encoding
1 = Enable channel; 0 = Disable channel
1 = 55 ms detection time for KP; 0 = 30 ms detection time for KP
1 = Enable MF tone detection after KP detection;
0 = MF tone detection always
Initial Configuration: The configuration of the M-986-
2A1 immediately after a reset will be as follows:
•
channel disabled
•
2-of-6 input/output
•
external serial and serial frame clocks.
Also, the M-986-2A1 will place a 00 hex on the
coprocessor port to indicate to the host processor that
it is working.
Transmit Tone Command
The transmit tone command allows the host processor
to transmit any two of the 6 R1 MF frequencies. The
format of the command depends on whether the M-
986 is configured for binary format or 2-of-6 format.
Coprocessor Port
Commands are written to the M-986 via the coproces-
sor port, and data indicating the received R1 MF tone
is read from the coprocessor port.
Writing to the Coprocessor Port:
The following
sequence describes writing a command to the M-986.
(1) The WR signal is driven low by the host processor.
(2) The RBLE (receive buffer latch empty) signal tran-
sitions to a logic high level.
(3) Data is written from D7-D0 to the receive buffer
latch (D7-D0) when the WR signal goes high.
(4) The RBLE signal transitions to a logic low level
after the M-986 reads the data. This signals the host
processor that the receive buffer is empty.
Note:
The RBLE should be low before writing to the
coprocessor.
Recieved Tone Detection
When a tone is detected by the M-986, the TBLF out-
put goes low, indicating reception of the tone to the
host processor. The host processor can determine
which tone was detected and which channel the tone
was detected on by reading data from the M-986
coprocessor port. The M-986 will return a single byte
indicating the tone received and the channel that the
tone was received on. The format of the returned byte
depends on whether the M-986 is configured for bina-
ry or 2-of-6 coding.
Reading the Coprocessor Port: The following
sequence describes reading received tone informa-
tion from the coprocessor port.
(1) The TBLF (transmit buffer latch full) port pin on the
M-986 goes low indicating the reception of a tone.
(2) The host processor detects the low logic level on
the TBLF pin either by polling a connected port pin or
by an interrupt.
(3) The host processor drives the RD signal low.
(4) The TBLF (transmit buffer latch full) signal transi-
tion to a logic high level.
Rev. 3
www.clare.com
3
M-986-2A1
(5) Data is driven onto D7-D0 by the M-986 until the
RD signal is driven high by the host processor.
Clock Characteristics and Timing
Internal Clock Option:
The internal oscillator is enabled
by connecting a crystal across X1 and X2/CLKIN. The
frequency of CLKOUT is one-fourth the crystal funda-
mental frequency. The crystal should be 20.48 MHz,
fundamental mode, and parallel resonant, with an
effective series resistance of 30 ohms, a power dissi-
pation of 1 mW, and be specified at a load capacitance
of 20 pF.
External Clock Option:
An external frequency source
can be used by injecting the frequency directly in
X2/CLKIN with X1 left unconnected. The external fre-
quency injected must conform to the specifications list-
ed in External Frequency Specifications table on page
6.
Flammability/Reliability Specifications
Reliability:
Flammability:
185 FITS failures/billion hours
Passes UL 94 V-0 tests
2 of 6 Coding Format
Byte
Bit 7
Transmit tone command
1
Receive tone return
0
CHN: 1 = channel 2; 0 = channel 1
R1 MF Frequencies:
Bit name
Frequency (Hz)
F6
F5
F4
1700
1500
1300
Bit 6
CHN
CHN
Bit 5
F6
F6
Bit 4
F5
F5
Bit 3
F4
F4
Bit 2
F3F2
F3F2
Bit 1
F1
F1
Bit 0
Bit name
F3
F2
F1
Frequency (Hz)
1100
900
700
Binary Coding Format
Byte
Bit 7
Transmit tone command
1
Receive tone return
0
CHN: 1 = channel 2; 0 = channel 1
R1 MF Frequencies:
ABCD Frequencies (Hz)
0000
0001
0010
0011
0100
0101
0110
0111
Tone off
700 & 900
700 & 1100
900 & 1100
700 & 1300
900 & 1300
1100 & 1300
700 & 1500
Bit 6
CHN
CHN
Bit 5
0
0
Bit 4
0
0
Bit 3
A
A
Bit 2
B
B
Bit 1
C
C
Bit 0
D
D
Name
-
Digit 1
Digit 2
Digit 3
Digit 4
Digit 5
Digit 6
Digit 7
ABCD
1000
1001
1010
1011
1100
1101
1110
1111
Frequencies (Hz)
900 & 1500
1100 & 1500
1300 & 1500
700 & 1700
900 & 1700
1100 & 1700
1300 & 1700
1500 & 1700
Name
Digit 8
Digit 9
Digit 0
ST3
ST1
KP
ST2
ST
Rev. 3
4
www.clare.com
M-986-2A1
Signal Description
Signal
D15-D8
D7-D0
TBLF
RBLE
HI/LO
BIO
RD
Pin
18-11
19-26
40
1
2
9
32
I/O/Z
I/O/Z
I/O/Z
O
O
I
I
I/O
Description
Unused. Leave open.
8-bit coprocessor latch.
Transmit buffer latch full flag.
Receive buffer latch empty flag.
Latch byte select pin. Tie low.
Unused. Leave open.
Used by the external processor to read from the coprocessor latch by driving the
RD line active (low), thus enabling the output latch to drive the latched data.
When the data has been read, the external device must bring the RD line high.
Unused. Leave open.
Microcomputer mode select pin. Tie low.
Coprocessor mode select pin. Tie low.
Reset input for initializing the device. When an active low is placed on RS pin for
a minimum of five clock cycles, RD and WR are forced high, and the data bus
(LD7 through LD0) goes to a high impedance state. The serial port clock and
transmit outputs also go to the high impedance state.
Used by the external processor to write data to the coprocessor port. To write
data the external processor drives the WR line low, places data on the data bus,
and then drives the WR line high to clock the data into the on-chip latch.
Watchdog signal. Toggles at least once every 10 milliseconds when the
processor is functioning properly. If the pin is not toggled at least once every 10
ms, the processor is lost and should be reset.
System clock output (one-fourth crystal/CLKIN frequency, nominally 5.12 MHz).
Ground pin.
5V supply pin.
Crystal output pin for internal oscillator. If the internal oscillator is not used, this
pin should be left unconnected.
Input pin to the internal oscillator (X2) from the crystal. Alternatively, an input pin
for the external oscillator (CLKIN).
Serial-port receive-channel inputs. 2.048 MHz serial data is received in the receive
registers via these pins. DR0 = channel 1; DR1 = channel 2.
8 kHz internal serial-port framing output. If internal clocking is selected,
serial-port transmit and receive operations occur simultaneously on an active
(high) FR framing pulse.
Serial-port transmit-channel outputs. 2.048 MHz serial data is transmitted from
the transmit registers on these pins. These outputs are in the high-impedance
state when not transmitting. DX0 = channel 1; DX1 = channel 2.
8 kHz external serial-port receive-framing input. If external clocking is selected,
data is received via the receive pins (DR1 and DR0) on the active (low) FSR input.
The falling edge of FSR initiates the receive process, and the rising edge causes
the M-986 to process the data.
2.048 MHz serial-port clock. Master clock for transmitting and receiving serial-
port data. Configured as an input in external clocking mode or output in internal
clocking mode. Reset (RS) forces SCLK to the high-impedance state.
8 kHz external serial-port transmit-framing input. If external clocking is enabled,
data is transmitted on the transmit pins (DX1, DX0) on the active (low) input. The
falling edge of FSX initiates the transmit process, and the rising edge causes the
M-986 to internally load data for the next cycle.
EXINT
MC
MC/PM
RS
5
3
27
4
I
I
I
I
WR
31
I/O
XF
28
O
CLKOUT
V
SS
V
CC
X1
X2/CLKIN
DR1 & DR0
FR
6
10
30
7
8
33 & 29
37
O
I
I
O
I
I
O
DX1 & DX0
36 & 35
O
FSR
39
I
SCLK
34
I/O/Z
FSX
38
I
Rev. 3
www.clare.com
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
