Standard Products
CT2553 / CT2554 / CT2555 / CT2556
Advanced Integrated MUX (AIM) Hybrid
for MIL-STD-1553
June 7, 2006
www.aeroflex.com/Avionics
FEATURES
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Second source compatible to the BUS-61553 / 4 / 5/ 6
Complete Integrated MUX Including:
- Low power dual transceiver
- BC / RTU / MT protocol
- 8K x 16 shared RAM
- Interrupt logic
Compatible with MIL-STD-1750 and other standard CPUs
DIP or Flatpack hybrid
Minimizes CPU overhead
Provides memory mapped 1553 interface
On-Line & Off-Line self-test
PCs development tools available
SEAFAC Tested
Designed for commercial, industrial and aerospace applications
MIL-PRF-38534 compliant circuit pending
Aeroflex is a class H & K MIL-PRF-38534 manufacturer
DESC SMD #5962–88692 approved
Packaging – Hermetic Metal
- 78 Pin, 2.1" x 1.87" x .25" Plug-In type package
- 82 Lead, 2.2" x 1.61" x .18" Flat package
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APPLICATIONS
The Aeroflex-Plainview CT2553 Advanced Integrated Mux (AIM) Hybrid is a complete MIL-STD-1553 Bus
Controller (BC), Remote Terminal Unit (RTU), and Bus Monitor (MT) device. Packaged in a single 78 pin DIP
package, the CT2553 contains dual low-power transceivers, complete BC / RTU / MT protocol logic, a
MIL-STD-1553-to-host interface unit and an 8K x 16 RAM.
Using an industry standard dual transceiver and standard status and control signals, the CT2553 simplifies system
integration at both the MIL-STD-1553 and host processor interface levels.
All 1553 operations are controlled through the CPU access to the shared 8K x 16 RAM. To ensure maximum
design flexibility, memory control lines are provided for attaching external RAM to the CT2553 Address and Data
Buses and for disabling internal memory; the total combined memory space can be expanded to 64K x16. All
MIL-STD-1553 transfers are entirely memory-mapped; thus the CPU interface requires minimal hardware and/or
software support.
The CT2553 operates over the full military -55°C to +125°C temperature range. Available screened to
MIL-STD883, the CT2553 is ideal for demanding military and industrial microprocessor to 1553 interface
applications.
See "Ordering Information" (last sheet) for CT2554, CT2555 & CT2556.
SCDCT2553 Rev E
GENERAL
The CT2553 is a complete MIL-STD-1553 bus interface
unit containing dual low-power transceivers; Bus
Controller (BC), Remote Terminal (RTU), and Bus
Monitor (MT) protocol logic; 8K x 16-bit pseudo dual
port RAM; and memory management arbitration control
circuitry. The host processor interface consists of
standard control and interrupt signals, memory expansion
capability and non-multiplexed address and data buses.
Control of the CT2553 is accomplished entirely through
the use of three internal registers and the shared RAM.
Transfers to and from the CT2553 are executed on a
word-by-word basis ensuring minimal wait time if
contention occurs.
The specific mods of operation (1553 BC/RT/MT) is
software programmable. Memory is configured into
unique control and data block areas based on the 1553
mode of operation. External registers are also supported
by the CT2553 for manipulation of user data. In addition,
the CT2553 provides dynamic, online and software
initiated self-test capabilities.
MEMORY MANAGEMENT
Memory can be configured to support two AREAs (A
and B), each with an independent sequential stack and
pointers for manipulating 1553 message and control data.
The CPU can access the shared RAM while 1553
message transfers are taking place. Arbitration of the
RAM is automatically implemented in a manner
transparent to the subsystem (See Figures 28-31).
Variable Length DATA BLOCKS are also stored in the
shared RAM and can be addressed by setting pointers
residing in Area A, Area B or both.
For BC/RTU operation, each area contains a Descriptor
Stack and Stack Pointer (See Figures 6 and 7). BC
operation further maintains a Message Count for each
area (number of 1553 messages per frame). RTU
operation maintains a data block address Look-Up Table
for each area. MT operation utilizes a single Stack
Pointer to indicate the starting address for storage of
received words and associated identification Words.
CURRENT AREA ASSIGNMENT/SWAPPING
Current area status (currently available to the 1553
terminal) is Software programmable by the host; the
unassigned area automatically assumes non-current area
status. Both areas are always addressable by the host.
Swapping of the Current Area can be done following
message transfers for user operations such as exception
handling or multiple buffering of 1553 data.
The host selects the Current Area by writing to the
CT2553’s Configuration Register with bit 13 set to the
appropriate logic level (0 for area A or 1 for area B).
Internal circuitry ensures that the swapping of Current
Area Status does not occur during an ongoing message
transfer (See Configuration Register).
INTERFACING
The CT2553 is compatible with most common
microprocessors including, but not limited to, the
Motorola 680 x 0, the Intel 808x, Zilog Z800x and
MIL-STD-1750 processors.
Interfacing the CT2553 to the MIL-STD-1553 Data Bus
requires two Q1553-2 pulse transformers and an external
16 MHz clock (See Figure 2). Tri-state buffers are used
to isolate the CPU's data and address lines.
External RAM can be used instead of or in conjunction
with the CT2553's internal 8K x 16 bits. The external
RAM used by the CT2553 can be any standard static
memory with an access time of < 55ns. The external
RAM can be expanded to 64K x 16.
Two control signals, MEMENA-IN (pin 69) and
MEMENMA-OUT (pin 31) are provided in addition to
the standard memory I/O signals for internal/external
memory access control (See Figures 3 - 5).
MEMEN-OUT and MEMEN-IN should be tied together
for Internal Memory Only configuration. Memory CS
signals can be generated for configurations using
external memory.
DESCRIPTOR STACK (BC/RTU)
The DESCRIPTOR STACK (DS) is divided into 64
entries. Each stack entry contains four words which refer
to one 1553 message. The Block Status Word (BSW)
indicates the physical bus on which the message was
received (RTU mode), reports whether or not an error
was detected during message transfer and indicates
message completion (See Figure 8).
The user-supplied Time Tag word is loaded at the start of
a message transfer and is updated at the end of the
transfer (See Time Tagging).
SCDCT2553 Rev E
Aeroflex Plainview
4
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