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CY25100
Field and Factory-Programmable Spread Spectrum
Clock Generator for EMI Reduction
Features
■
Benefits
■
■
Wide operating output (SSCLK) frequency range
❐
3–200 MHz
Programmable spread spectrum with nominal 31.5-kHz
modulation frequency
❐
Center spread: ±0.25% to ±2.5%
❐
Down spread: –0.5% to –5.0%
Input frequency range
❐
External crystal: 8–30 MHz fundamental crystals
❐
External reference: 8–166 MHz Clock
Integrated phase-locked loop (PLL)
Field-programmable
❐
CY25100SCF and CY25100SIF, 8-pin SOIC
❐
CY25100ZCF and CY25100ZIF, 8-pin TSSOP
Programmable crystal load capacitor tuning array
Low cycle-to-cycle jitter
3.3V operation
Commercial and Industrial operation
Spread Spectrum On/Off function
Power down or Output Enable function
Services most PC peripherals, networking, and consumer
applications.
Provides wide range of spread percentages for maximum
electromagnetic interference (EMI) reduction, to meet
regulatory agency electromagnetic compliance (EMC) require-
ments. Reduces development and manufacturing costs and
time-to-market.
Eliminates the need for expensive and difficult to use
higher-order crystals.
Internal PLL to generate up to 200 MHz output. Able to generate
custom frequencies from an external crystal or a driven source.
In-house programming of samples and prototype quantities is
available using the CY3672 programming kit and
CY3690 (TSSOP) or CY3691 (SOIC) socket adapter.
Production quantities are available through Cypress’s
value-added distribution partners or by using third-party
programmers from BP Microsystems, HiLo Systems, and
others.
Enables fine-tuning of output clock frequency by adjusting
C
Load
of the crystal. Eliminates the need for external C
Load
capacitors.
Suitable for most PC, consumer, and networking applications
Application compatibility in standard and low-power systems
Provides ability to enable or disable spread spectrum with an
external pin.
Enables low-power state or output clocks to High-Z state.
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Logic Block Diagram
RFB
3
XIN
C
XIN
PLL
with
MODULATION
CONTROL
6
2
XOUT
C
XOUT
PROGRAMMABLE
CONFIGURATION
OUTPUT
DIVIDERS
and
MUX
REFCLK
7
4
PD# or OE
8
SSON#
1
VDD
5
VSS
SSCLK
Cypress Semiconductor Corporation
Document #: 38-07499 Rev. *E
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised June 13, 2008
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CY25100
Pinouts
Figure 1. CY25100 8-Pin SOIC/TSSOP
1 VDD
SSON# 8
SSCLK 7
2
XOUT
3 XIN/CLKIN
REFCLK 6
4 PD#/OE
VSS 5
Pin Description
Pin
1
2
3
4
VDD
XOUT
XIN/CLKIN
PD#/OE
Name
3.3V power supply.
Crystal output. Leave this pin floating if external clock is used.
Crystal input or reference clock input.
Power down pin: Active LOW. If PD# = 0, the PLL and Xtal are powered down, and outputs are
weakly pulled low.
Output Enable pin: Active HIGH. If OE = 1, SSCLK and REFCLK are enabled. User has the
option of choosing either PD# or OE function.
Power supply ground.
Buffered reference output.
Spread spectrum clock output.
Spread spectrum control. 0 = Spread on. 1 = Spread off.
Description
5
6
7
8
VSS
REFCLK
SSCLK
SSON#
General Description
The CY25100 is a Spread Spectrum Clock Generator (SSCG) IC
used for the purpose of reducing EMI found in today’s
high-speed digital electronic systems.
The device uses a Cypress proprietary PLL and Spread
Spectrum Clock (SSC) technology to synthesize and modulate
the frequency of the input clock. By frequency modulating the
clock, the measured EMI at the fundamental and harmonic
frequencies are greatly reduced. This reduction in radiated
energy can significantly reduce the cost of complying with
regulatory agency (EMC) requirements and improve
time-to-market without degrading system performance.
The CY25100 uses a factory/field-programmable configuration
memory array to synthesize output frequency, spread%, crystal
load capacitor, reference clock output on/off, spread spectrum
on/off function and PD#/OE options.
Table 1.
Pin Function
Pin Name
Pin#
Unit
Program Value
Input
Frequency
Total Xtal
Load
Capacitance
3 and 2
pF
Output
Frequency
SSCLK
7
MHz
Spread Percent
(0.5% – 5%,
0.25% Intervals)
SSCLK
7
%
ENTER DATA
Reference
Output
REFOUT
6
On or Off
ENTER DATA
Power down or Frequency
Output Enable Modulation
PD#/OE
4
Select PD# or OE
ENTER DATA
SSCLK
7
kHz
31.5
The spread% is programmed to either center spread or down
spread with various spread percentages. The range for center
spread is from ±0.25% to ±2.50%. The range for down spread is
from –0.5% to –5.0%. Contact the factory for smaller or larger
spread % amounts if required.
The input to the CY25100 can be either a crystal or a clock
signal. The input frequency range for crystals is 8–30 MHz, and
for clock signals is 8–166 MHz.
The CY25100 has two clock outputs, REFCLK and SSCLK. The
non-spread spectrum REFCLK output has the same frequency
as the input of the CY25100. The frequency modulated SSCLK
output can be programmed from 3–200 MHz.
The CY25100 products are available in an 8-Pin SOIC and
TSSOP packages with commercial and industrial operating
temperature ranges.
XIN and XOUT XIN and XOUT
3 and 2
MHz
ENTER DATA ENTER DATA ENTER DATA
Document #: 38-07499 Rev. *E
Page 2 of 13
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CY25100
Programming Description
Field-Programmable CY25100
The CY25100 is programmed at the package level, that is, in a
programmer socket. The CY25100 is flash-technology based, so
the parts can be reprogrammed up to 100 times. This allows for
fast and easy design changes and product updates, and elimi-
nates any issues with old and out-of-date inventory.
Samples and small prototype quantities can be programmed on
the CY3672 programmer with CY3690 (TSSOP) or CY3691
(SOIC) socket adapter.
Product Functions
Input Frequency (XIN, pin 3 and XOUT
,
pin 2)
The input to the CY25100 can be a crystal or a clock. The input
frequency range for crystals is 8 to 30 MHz, and for clock signals
is 8 to 166 MHz.
C
XIN
and C
XOUT
(pin 3 and pin 2)
The load capacitors at Pin 1 (C
XIN
) and Pin 8 (C
XOUT
) can be
programmed from 12 pF to 60 pF with 0.5-pF increments. The
programmed value of these on-chip crystal load capacitors are
the same (XIN = XOUT = 12 to 60 pF).
The required values of
C
XIN
and C
XOUT
can be calculated using
the following formula:
C
XIN
= C
XOUT
= 2C
L
– C
P
where C
L
is the crystal load capacitor as specified by the crystal
manufacturer and C
P
is the parasitic PCB capacitance.
For example, if a fundamental 16 MHz crystal with C
L
of 16 pF is
used and C
P
is 2 pF, C
XIN
and C
XOUT
can be calculated as:
C
XIN
= C
XOUT
= (2 x 16) – 2 = 30 pF.
If using a driven reference, set C
XIN
and C
XOUT
to the minimum
value 12 pF.
CyberClocks™ Online Software
CyberClocks™ Online Software is a web-based software appli-
cation that allows the user to custom-configure the CY25100. All
the parameters in
Table 1
given as “Enter Data” can be
programmed into the CY25100. CyberClocks Online outputs an
industry-standard JEDEC file used for programming the
CY25100. CyberClocksOnline is available at www.cyberclock-
sonline.com website through user registration. To register, fillout
the registration form and make sure to check the “non-standard
devices” box. For more information on the registration process
refer to CY3672 data sheet
For information regarding Spread Spectrum software
programming solutions, please contact your local Cypress Sales
or Field Application Engineer (FAE), representative for details.
Output Frequency, SSCLK Output (SSCLK, pin 7)
The modulated frequency at the SSCLK output is produced by
synthesizing the input reference clock. The modulation can be
stopped by SSON# digital control input (SSON# = HIGH, no
modulation). If modulation is stopped, the clock frequency is the
nominal value of the synthesized frequency without modulation
(spread % = 0). The range of synthesized clock is from
3–200 MHz.
CY3672 FTG Programming Kit and CY3690/CY3691
Socket Adapter
The Cypress CY3672 FTG programmer and CY3690/CY3691
Socket Adapter are needed to program the CY25100. The
CY3690 enables user to program CY25100ZCF and
CY25100ZIF (TSSOP) and CY3691 gives the user the ability to
program CY25100SCF and CY25100SIF (SOIC). Each socket
adapter comes with small prototype quantities of CY25100. The
CY3690/CY3691 is a separate orderable item, so the existing
users of the CY3672 FTG development kit or CY3672-PRG
programmer need to order only the socket adapters to program
the CY25100.
Spread Percentage (SSCLK, pin 7)
The SSCLK spread can be programmed at any percentage value
from ±0.25% to ±2.5% for Center Spread and from –0.5% to
–5.0% Down Spread.
Reference Output (REFOUT, pin 6)
The reference clock output has the same frequency and the
same phase as the input clock. This output can be programmed
to be enabled (clock on) or disabled (High-Z, clock off). If this
output is not needed, it is recommended that users request the
disabled (High-Z, Clock Off) option.
Factory-Programmable CY25100
Factory programming is available for volume manufacturing by
Cypress. All requests must be submitted to the local Cypress
Field Application Engineer (FAE) or sales representative. A
sample request form (refer to “CY25100 Sample Request Form”
at
www.cypress.com)
must be completed. After the request has
been processed, you will receive a new part number, samples,
and data sheet with the programmed values. This part number
will be used for additional sample requests and production
orders.
Additional information on the CY25100 can be obtained from the
Cypress web site at
www.cypress.com.
Frequency Modulation
The frequency modulation is programmed at 31.5 kHz for all
SSCLK frequencies from 3 to 200 MHz. Contact the factory if a
higher-modulation frequency is required.
Power down or Output Enable (PD# or OE, pin 4):
The part can be programmed to include either PD# or OE
function. PD# function powers down the oscillator and PLL. The
OE function disables the outputs.
Document #: 38-07499 Rev. *E
Page 3 of 13
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CY25100
Absolute Maximum Rating
Supply Voltage (V
DD
)........................................ –0.5 to +7.0V
DC Input Voltage ......................................–0.5V to V
DD
+ 0.5
Storage Temperature (Non-condensing) .... –55°C to +125°C
Junction Temperature ................................ –40°C to +125°C
Data Retention at Tj = 125°C ................................> 10 years
Package Power Dissipation...................................... 350 mW
Static Discharge Voltage.......................................... > 2000V
(per MIL-STD-883, Method 3015)
Recommended Crystal Specifications
Parameter
F
NOM
C
LNOM
R
1
R
3
/R
1
DL
Description
Nominal Crystal Frequency
Nominal Load Capacitance
Equivalent Series Resistance (ESR)
Internal load caps
Fundamental mode
Comments
Parallel resonance, fundamental mode, AT cut
Min
8
6
–
3
–
Typ.
–
–
–
–
0.5
Max
30
30
25
–
2
Unit
MHz
pF
Ω
–
mW
Ratio of Third Overtone Mode ESR to Ratio used because typical R
1
values are much
Fundamental Mode ESR
less than the maximum spec
Crystal Drive Level
No external series resistor assumed
Operating Conditions
Parameter
V
DD
T
A
C
LOAD
F
ref
Supply Voltage
Ambient Commercial Temperature
Ambient Industrial Temperature
Max. Load Capacitance at pin 6 and pin 7
External Reference Crystal
(Fundamental tuned crystals only)
External Reference Clock
F
SSCLK
F
REFCLK
F
MOD
T
PU
SSCLK output frequency, C
LOAD
= 15 pF
REFCLK output frequency, C
LOAD
= 15 pF
Spread Spectrum Modulation Frequency
Power up time for all VDDs to reach minimum specified voltage (power ramp must be
monotonic)
Description
Min
3.13
0
–40
–
8
8
3
8
30.0
0.05
Typ.
3.30
–
–
–
–
–
–
–
31.5
–
Max
3.45
70
85
15
30
166
200
166
33.0
500
Unit
V
°C
°C
pF
MHz
MHz
MHz
MHz
kHz
ms
DC Electrical Characteristics
Parameter
I
OH
I
OL
V
IH
V
IL
I
IH
I
IL
I
OZ
C
XIN
or
C
XOUT[1]
C
IN
[1]
Description
Output High Current
Output Low Current
Input High Voltage
Input Low Voltage
Input High Current, PD#/OE and
SSON# pins
Condition
V
OH
= V
DD
– 0.5, V
DD
= 3.3V (source)
V
OL
= 0.5, V
DD
= 3.3V (sink)
CMOS levels, 70% of V
DD
CMOS levels, 30% of V
DD
V
in
= V
DD
Min
10
10
0.7V
DD
–
–
–
–10
–
–
–
Typ.
12
12
–
–
–
–
Max
Unit
mA
mA
V
DD
0.3V
D
D
V
V
μA
μA
μA
pF
pF
pF
10
10
10
Input Low Current, PD#/OE and SSON# V
in
= V
SS
pins
Output Leakage Current
Programmable Capacitance at pin 2
and pin 3
Input Capacitance at pin 4 and pin 8
Three-state output, PD#/OE = 0
Capacitance at minimum setting
Capacitance at maximum setting
Input pins excluding XIN and XOUT
12
60
5
–
–
7
Note
1. Guaranteed by characterization, not 100% tested.
Document #: 38-07499 Rev. *E
Page 4 of 13
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