SED1651
SED1651
LOW-POWER 100-BIT LCD COMMON DRIVER
s
DESCRIPTION
The SED1651 is a 100-output dot matrix LCD common (row) driver for driving high-capacity LCD panels
at duty cycles higher than 1/64 (up to 1/300). The LSI has a wide range of the LCD driving voltages,
and has its maximum drive voltage, VO, isolated from V
DD
for the flexibility of bias voltage generation.
The SED1651 is used in conjunction with the SED1648 (80-output segment driver) or the SED1640 (80-
bit segment driver) to drive a large-capacity dot matrix LCD panel.
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FEATURES
•
Low-power CMOS technology
•
100-bit common (row) driver
•
Low output impedance ..................... 750Ω (typ)
•
Duty cycle ..................................... 1/64 to 1/300
•
Ability to adjust offset bias of the LCD relative to
V
DD
•
Non-biased display off function
•
Pin selection of the output shift direction
•
LCD voltage ...................................... –8 to –28V
•
Supply voltage .................................. 2.7 to 5.5V
•
Package .......................... Slim Al pad DIE (D )
OA
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SYSTEM BLOCK DIAGRAM
D0 ~ D3
XSCL
LP, FR
YSCL
YD
LCD
CONTR
SED1648
80
SED1651
100
SED1648
80
160 x 200 dots
DUTY: 1/200
SED1651
100
783
SED1651
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BLOCK DIAGRAM
O0
O 99
V0
V1
V4
V5
FR
LCD Driver
100 bits
V
SS
V
DD
DI01
YSCL
SHL
DSPOFF
SEL
Level Shifter
100 bits
Bidirectional Shift Register
50
×
2 bits
DI3 DIO2
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BLOCK DESCRIPTION
Enable Shift Register
•
This is a bidirectional shift register used for transmitting common data. The shift register has a 50
×
2 bit
structure, and is selectable to 50
×
2 bits or 100 bits depending on the setting of SEL.
When the 50
×
2 bit configuration is selected, the input for the second 50 bit shift register is DI3.
•
•
Level Shifter
The level shifter is a level interface circuit which converts the signal voltage level from a logic circuit level to
the LC driver voltage level.
LCD Driver
The LCD driver outputs the LC drive voltage.
The relationship between the display blanking signal DSPOFF, the contents of the shift register, the AC signal
FR, and the On output voltage is as follows:
DSPOFF
Contents of Shift Register
H
H
L
L
—
FR
H
L
H
L
—
784
O Output Voltage
V5
V0
V1
V4
V0
(Select level)
(Non-select level)
—
SED1651
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PIN DESCRIPTION
Pin Name
O0 to O99
DIO1
DIO2
DI3
SEL
YSCL
SHL
I/O
O
I/O
Function
Common (row) output to drive LC.
Output transition occurs on falling edge of YSCL.
50
×
2 bit bi-directional shift register serial data I/O.
This is set to input or output depending on the level of the SHL input.
Output transition occurs on falling edge of YSCL.
I
I
I
I
Scan pulse input terminal of the 50
×
2 structure.
When SEL = L, DI3 = V
SS
or GND.
Bi-directional shift register operating mode select input
H: 50
×
2 (DI3 input) L: 100
Serial data shift clock input (shifts scan data on falling edge).
Shift direction select and DIO terminal I/O control input.
SHL
L
H
0
99
→
→
O Output Shift Direction
49
50
50
49
→
→
99
0
DIO
1
2
I
O
O
I
No. of
Pins
100
2
1
1
1
1
When SEL = “H”, the DI3 input is input to O50 (SHL = “L”) or O49 (SHL = “H”).
When SEL = “L”, the DI3 input is ignored and the DIO input is continuously
shifted.
DSPOFF
FR
V
DD
, V
SS
I
I
Power
LC display blanking control input. A low level clears the shift register,
immediately causing all common outputs to go to V0.
LC drive output AC signal input.
Power source for logic:
V
DD
: 0V (GND)
V
SS
: –2.7 to –5.5V
LC Drive Circuit Power:
V5: –8 to –28V
V
DD
≥V0 ≥
V1 > V4
≥
V5
Total 119
1
1
3
V0, V1,
V4, V5
Power
8
785
SED1651
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ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
•
Parameter
Power voltage (1)
Power voltage (2)
Power voltage (3)
Input voltage
Output voltage
Output current (1)
Output current (2)
Operating temperature
Storage temperature (1)
Symbol
V
SS
V5
V0, V1, V4
VI
VO
IO
IOCOM
Topr
Tstg1
Condition
–7.0 to +0.3
–30.0 to +0.3
V5 – 0.3 to + 0.3
V
SS
– 0.3 to + 0.3
V
SS
– 0.3 to + 0.3
20
20
–40 to +85
–65 to +150
Unit
V
V
V
V
V
mA
mA
°C
°C
Notes:
*1. The voltages are all relative to V
DD
= 0V.
*2. Ensure that the relationship between V0, V1, V4, and V5 is always as follows: V
DD
≥
V0
≥
V1
≥
V4
≥
V5.
System Side
V
CC
5V
GND
V
SS
V
DD
–5V
–28V
V4
V5
*3. The LSI may be permanently damaged if the logic system power is floating or V
SS
is less than or equal to –2.6V when
power is applied to the LC drive circuit system. Special caution must be paid to the power sequences when turning
the power on and off.
V
DD
V0
V1
786
SED1651
•
DC Electrical Characteristics
Parameter
Symbol
V
SS
V5
V5
V0
V1
V4
V
IH
V
IL
V
OH
V
OL
I
LI
I
LI/O
I
DDS
R
COM
I
OH
= –0.3mA
I
OL
= 0.3mA
V
SS
≤
V
IN
≤
0V
V
SS
≤
V
IN
≤
0V
V5 = –12.0 to –28.0V
V
IH
= V
DD
, V
IL
= V
SS
∆|V
ON
| = 0.5V, V0 = V
DD
,
V1 = –1.5V, V4 = –18.5V,
V5 = –20.0V
V
SS
= –5.0V, V
IH
= V
DD
,
V
IL
= V
SS
, f
YSCL
= 12KHz,
Frame frequency = 60 Hz,
Input data: 1/200;
Ta = 25°C, Each duty
cycle is “H”, no load
V
SS
= –3.0V; other
parameters are the same
as for V
SS
= –5.0V
Function operation
Conditions
Unless otherwise specified, V
DD
= V0 = 0V,
V
SS
= –5.5 to –2.7V, T
a
= –40 to 85°C
Applicable Pins
V
SS
V5
V5
V0
V1
V4
DIO1, DIO2, FR,
YSCL, SHL, DI3,
DSPOFF, SEL
Min
–5.5
–28.0
—
–2.5
2/9
×
V5
V5
0.2
×
V
SS
—
V
DD
– 0.4
—
—
—
—
—
Typ
–5.0
—
—
—
—
—
—
—
—
—
—
—
0.75
Max
–2.7
–12.0
–8.0
0
V
DD
7/9
×
V5
—
0.8
×
V
SS
—
V
SS
+ 0.4
2.0
5.0
25
1.0
Unit
V
V
V
V
V
V
V
V
V
µA
µA
µA
KΩ
Power voltage (1)
Recommended operating
voltage
Possible operating
voltage
Power voltage (2)
Power voltage (3)
Power voltage (4)
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
Input leakage current
I/O leakage current
Static current
Output resistance
DIO1, DIO2
YSCL, SHL, DI3,
DSPOFF, FR, SEL
DIO1, DIO2
V
DD
O0 to O99
Average operating
consumption current (1)
I
SS1
V
SS
—
7
15
µA
—
5
10
µA
Average operating
consumption current (2)
I
SS2
V
SS
= –5.0V, V0 = 0V,
V1 = –1.5V, V4 = –18.5V,
VEE =V5 = –20.0V;
other parameters are
the same as for I
SS1
T
a
= 25°C
V5
—
7
15
µA
Input terminal capacitance
I/O terminal capacitance
C
I
C
I/O
YSCL, SHL, SEL,
DSPOFF, FR, DI3
—
—
—
—
8
15
pF
pF
DIO1, DIO2
787
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