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GS8342S09AE-333IS: 产品描述DDR SRAM, 4MX9, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, MO-216CAB-1, FPBGA-165; 产品类别存储存储; 文件大小2MB，共37页; 制造商GSI Technology; 官网地址http://www.gsitechnology.com/

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GS8342S09AE-333IS概述

DDR SRAM, 4MX9, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, MO-216CAB-1, FPBGA-165

GS8342S09AE-333IS规格参数

参数名称	属性值
是否Rohs认证	不符合
厂商名称	GSI Technology
零件包装代码	BGA
包装说明	LBGA,
针数	165
Reach Compliance Code	unknown
ECCN代码	3A991.B.2.B
最长访问时间	0.45 ns
其他特性	PIPELINED ARCHITECTURE
JESD-30 代码	R-PBGA-B165
长度	17 mm
内存密度	37748736 bit
内存集成电路类型	DDR SRAM
内存宽度	9
功能数量	1
端子数量	165
字数	4194304 words
字数代码	4000000
工作模式	SYNCHRONOUS
最高工作温度	85 °C
最低工作温度	-40 °C
组织	4MX9
封装主体材料	PLASTIC/EPOXY
封装代码	LBGA
封装形状	RECTANGULAR
封装形式	GRID ARRAY, LOW PROFILE
并行/串行	PARALLEL
峰值回流温度（摄氏度）	NOT SPECIFIED
认证状态	Not Qualified
座面最大高度	1.5 mm
最大供电电压 (Vsup)	1.9 V
最小供电电压 (Vsup)	1.7 V
标称供电电压 (Vsup)	1.8 V
表面贴装	YES
技术	CMOS
温度等级	INDUSTRIAL
端子形式	BALL
端子节距	1 mm
端子位置	BOTTOM
处于峰值回流温度下的最长时间	NOT SPECIFIED
宽度	15 mm

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Preliminary

GS8342S08/09/18/36AE-333/300/250/200/167

165-Bump BGA

Commercial Temp

Industrial Temp

Features

• Simultaneous Read and Write SigmaSIO™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write (x36, x18, and x9) and Nybble Write (x8) function

• DLL circuitry for wide output data valid window and future

frequency scaling

• Burst of 2 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ mode pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

• Pin-compatible with future 72Mb and 144Mb devices

36Mb Burst of 2

DDR SigmaSIO-II SRAM

167 MHz–333 MHz

1.8 V V

1.8 V and 1.5 V I/O

Bottom View

165-Bump, 15 mm x 17 mm BGA

1 mm Bump Pitch, 11 x 15 Bump Array

JEDEC Std. MO-216, Variation CAB-1

SigmaRAM™ Family Overview

GS8342S08/09/18/36AE are built in compliance with the

SigmaSIO-II SRAM pinout standard for Separate I/O

synchronous SRAMs. They are 37,748,736-bit (36Mb)

SRAMs. These are the first in a family of wide, very low

voltage HSTL I/O SRAMs designed to operate at the speeds

needed to implement economical high performance

networking systems.

Clocking and Addressing Schemes

A Burst of 2 SigmaSIO-II SRAM is a synchronous device. It

employs dual input register clock inputs, K and K. The device

also allows the user to manipulate the output register clock

input quasi independently with dual output register clock

inputs, C and C. If the C clocks are tied high, the K clocks are

routed internally to fire the output registers instead. Each Burst

of 2 SigmaSIO-II SRAM also supplies Echo Clock outputs,

CQ and CQ, which are synchronized with read data output.

When used in a source synchronous clocking scheme, the Echo

Clock outputs can be used to fire input registers at the data’s

destination.

Because Separate I/O Burst of 2 RAMs always transfer data in

two packets, A0 is internally set to 0 for the first read or write

transfer, and automatically incremented by 1 for the next

transfer. Because the LSB is tied off internally, the address

field of a Burst of 2 RAM is always one address pin less than

the advertised index depth (e.g., the 2M x 18 has a 1M

addressable index).

Parameter Synopsis

- 333

tKHKH

tKHQV

3.0 ns

0.45 ns

-300

3.3 ns

0.45 ns

-250

4.0 ns

0.45 ns

-200

5.0 ns

0.45 ns

-167

6.0 ns

0.5 ns

Rev: 1.00 6/2006

1/37

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8342S09AE-333IS

GS8342S09AE-333IS概述

GS8342S09AE-333IS规格参数

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