Preliminary
GS8662T06/20/38BD-550/500/450/400/350
GS8662T11BD-500/450/400/350
165-Bump BGA
Commercial Temp
Industrial Temp
Features
• 2.5 Clock Latency
• Simultaneous Read and Write SigmaDDR
TM
Interface
• JEDEC-standard pinout and package
• Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 2 Read and Write
• On-Die Termination (ODT) on Data (D), Byte Write (BW),
and Clock (K, K) inputs
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• Data Valid Pin (QVLD) Support
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
72Mb SigmaDDR
TM
-II+
Burst of 2 SRAM
550 MHz–350 MHz
1.8 V V
DD
1.8 V or 1.5 V I/O
SRAMs. The GS8662T06/11/20/38BD SigmaDDR-II+
SRAMs are just one element in a family of low power, low
voltage HSTL I/O SRAMs designed to operate at the speeds
needed to implement economical high performance
networking systems.
Clocking and Addressing Schemes
The GS8662T06/11/20/38BD SigmaDDR-II+ SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Because Common I/O SigmaDDR-II+ RAMs always transfer
data in two packets, A0 is internally set to 0 for the first read
or write transfer, and automatically incremented by 1 for the
next transfer. Because the LSB is tied off internally, the
address field of a SigmaDDR-II+ B2 RAM is always one
address pin less than the advertised index depth (e.g., the 4M x
18 has a 2M addressable index).
SigmaDDR-II™ Family Overview
The GS8662T06/11/20/38BD are built in compliance with the
SigmaDDR-II+ SRAM pinout standard for Common I/O
synchronous SRAMs. They are 75,497,472-bit (72Mb)
Parameter Synopsis (x8/x18/x36)
-550
tKHKH
tKHQV
1.81 ns
0.29ns
-500
2.0 ns
0.33 ns
-450
2.2 ns
0.37 ns
-400
2.5 ns
0.45 ns
-350
2.86 ns
0.45 ns
Parameter Synopsis (x9)
-500
tKHKH
tKHQV
2.0 ns
0.33 ns
-450
2.2 ns
0.37ns
-400
2.5 ns
0.45 ns
-350
2.86 ns
0.45 ns
Rev: 1.01 11/2010
1/35
© 2010, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8662T06/20/38BD-550/500/450/400/350
GS8662T11BD-500/450/400/350
2M x 36 SigmaDDR-II+ SRAM—Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
2
NC/SA
(144Mb)
DQ27
NC
DQ29
NC
DQ30
DQ31
V
REF
NC
NC
DQ33
NC
DQ35
NC
TCK
3
SA
DQ18
DQ28
DQ19
DQ20
DQ21
DQ22
V
DDQ
DQ32
DQ23
DQ24
DQ34
DQ25
DQ26
SA
4
R/W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
BW2
BW3
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
QVLD
ODT
7
BW1
BW0
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
LD
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
SA
NC/SA
(288Mb)
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
10
SA
NC
DQ17
NC
DQ15
NC
NC
V
REF
DQ13
DQ12
NC
DQ11
NC
DQ9
TMS
11
CQ
DQ8
DQ7
DQ16
DQ6
DQ5
DQ14
ZQ
DQ4
DQ3
DQ2
DQ1
DQ10
DQ0
TDI
11 x 15 Bump BGA—13 x 15 mm
2
Body—1 mm Bump Pitch
Notes:
1. BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17; BW2 controls writes to DQ18:DQ26; BW3 controls writes to
DQ27:DQ35
2. Pins A2 and B9 are the expansion addresses.
Rev: 1.01 11/2010
2/35
© 2010, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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