Y2280
CY2280
100 MHz Pentium
®
II Clock Synthesizer/Driver with Spread
Spectrum for Mobile or Desktop PCs
Features
• Mixed 2.5V and 3.3V operation
• Clock solution for Pentium® II, and other similar
processor-based motherboards
— Four 2.5V CPU clocks up to 100 MHz
— Eight 3.3V sync. PCI clocks, one free-running
— Two 3.3V 48-MHz USB clocks
— Three 3.3V Ref. clocks at 14.318 MHz
— Two 2.5V APIC clocks at 14.318 MHz or PCI/2
• EMI control
— Spread spectrum clocking
— Factory-EPROM programmable spread spectrum
margin
— Factory-EPROM programmable output drive and
slew rate
• Factory-EPROM programmable CPU clock frequencies
for custom configurations
• Available in space-saving 48-pin SSOP package
Table 1.
Functional Description
The CY2280 is a Spread Spectrum clock synthesizer/driver for
a Pentium II, or other similar processor-based PC requiring
100-MHz support. All of the required system clocks are
provided in a space-saving 48-pin SSOP package. The
CY2280 can be used with the CY231x for a total solution for
systems with SDRAM.
The CY2280 provides the option of spread spectrum clocking
on the CPU and PCI clocks for reduced EMI. A downspread
percentage is introduced when the SEL_SS input is asserted.
The device can be run without spread spectrum when the
SEL_SS input is deasserted. The percentage of spreading is
EPROM-programmable to optimize EMI-reduction.
The CY2280 has power-down, CPU stop, and PCI stop pins
for power management control. The signals are synchronized
on-chip, and ensure glitch-free transitions on the outputs.
When the CPU_STOP input is asserted, the CPU clock
outputs are driven LOW. When the PCI_STOP input is
asserted, the PCI clock outputs (except the free-running PCI
clock) are driven LOW. When the PWR_DWN pin is asserted,
the reference oscillator and PLLs are shut down, and all
outputs are driven LOW.
CY2280 Selector Guide
.
CY2280 Configuration Options
Clock Outputs
–1
4
8
2
2
—
3
1.5 4.0 ns
—
N/A
-1
-2
CPU_STOP
XTALIN
XTALOUT
14.318
MHz
OSC.
CPU
PLL
Divider
STOP
LOGIC
–11S
4
8
2
2
—
3
1.5 4.0 ns
—
0.6%
–21S
4
8
2
—
2
3
1.5 4.0 ns
2.0–4.5 ns
0.6%
CPU (66.6, 100 MHz)
PCI (CPU/2, CPU/3)
USB (48 MHz)
APIC (14.318 MHz)
APIC (PCI/2)
Reference (14.318 MHz)
CPU-PCI delay
CPU-APIC delay
Spread Spectrum (Downspread)
Logic Block Diagram
APIC [0:1]
V
DDAPIC
REF [0-2]
V
DDREF
CPUCLK [0-3]
V
DDCPU
PCICLK_F
PWR_DWN
SEL0
SEL1
SEL100
SEL_SS
PCI_STOP
SYS PLL
Delay
STOP
LOGIC
EPROM
V
DDPCI
PCI [1-7]
V
DDPCI
USBCLK [0:1]
V
DDUSB
Rev 1.0, November 25, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
Page 1 of 11
www.SpectraLinear.com
CY2280
Pin Configurations
REF0
REF1
V
SS
XTALIN
XTALOUT
V
SS
PCICLK_F
PCICLK1
V
DDPCI
PCICLK2
PCICLK3
V
SS
PCICLK4
PCICLK5
V
DDPCI
PCICLK6
PCICLK7
V
SS
AV
DD
V
SS
V
DDUSB
USBCLK0
USBCLK1
V
SS
1
2
3
4
5
6
7
48-pin SSOP (Top View)
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
V
DDREF
REF2
V
DDAPIC
APIC0
APIC1
V
SS
RESERVED
V
DDCPU
CPUCLK0
CPUCLK1
V
SS
V
DDCPU
CPUCLK2
CPUCLK3
V
SS
AV
DD
V
SS
PCI_STOP
CPU_STOP
PWR_DWN
N/C
SEL0
SEL1
SEL100
REF0
REF1
V
SS
XTALIN
XTALOUT
V
SS
PCICLK_F
PCICLK1
V
DDPCI
PCICLK2
PCICLK3
V
SS
PCICLK4
PCICLK5
V
DDPCI
PCICLK6
PCICLK7
V
SS
AV
DD
V
SS
V
DDUSB
USBCLK0
USBCLK1
V
SS
1
2
3
4
5
6
7
48-pin SSOP (Top View)
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
V
DDREF
REF2
V
DDAPIC
APIC0
APIC1
V
SS
RESERVED
V
DDCPU
CPUCLK0
CPUCLK1
V
SS
V
DDCPU
CPUCLK2
CPUCLK3
V
SS
AV
DD
V
SS
PCI_STOP
CPU_STOP
PWR_DWN
SEL_SS
SEL0
SEL1
SEL100
CY2280-1
CY2280-11S
CY2280-21S
Pin Summary
Name
V
DDPCI
V
DDUSB
V
DDREF
V
DDAPIC
V
DDCPU
AV
DD
V
SS
XTALIN
[1]
XTALOUT
[1]
PCI_STOP
CPU_STOP
PWR_DWN
SEL_SS
N/C
SEL0
SEL1
SEL100
CPUCLK[0:3]
PCICLK[1:7]
PCICLK_F
APIC[0:1]
REF[0:2]
USBCLK[0:1]
RESERVED
Pins
15, 9
21
48
46
41, 37
33, 19
4
5
31
30
29
28
28
27
26
25
40, 39, 36, 35
8, 10, 11, 13, 14, 16, 17
7
45, 44
1, 2, 47
22, 23
42
Description
3.3V Digital voltage supply for PCI clocks
3.3V Digital voltage supply for USB clocks
3.3V Digital voltage supply for REF clocks
2.5V Digital voltage supply for APIC clocks
2.5V Digital voltage supply for CPU clocks
Analog voltage supply, 3.3V
Reference crystal input
Reference crystal feedback
Active LOW control input to stop PCI clocks
Active LOW control input to stop CPU clocks
Active LOW control input to power down device
Spread spectrum select input (-11S and -21S options)
Spread spectrum select input (-1 option)
CPU frequency select input, bit 0 (see Function Table)
CPU frequency select input, bit 1 (see Function Table)
CPU frequency select input, selects between 100 MHz and 66.6 MHz
(see Function Table)
CPU clock outputs
PCI clock outputs, at one-half or one-third the CPU frequency of 66.6 MHz
or 100 MHz respectively
Free-running PCI clock output
APIC clock outputs
3.3V Reference clock outputs
USB clock outputs
Reserved
Page 2 of 11
3, 6, 12, 18, 20, 24, 32, 34, 38, 43 Ground
Rev 1.0, November 25, 2006
Note:
1. For best accuracy, use a parallel-resonant crystal, C
LOAD
= 18 pF.
CY2280
Function Table (-11S Option)
SEL100 SEL1 SEL0
0
0
0
0
0
1
1
1
1
1
0
0
1
1
1
0
0
1
1
1
0
1
0
1
1
0
1
0
1
1
SEL_SS
[2]
N/A
N/A
N/A
0 (downspread)
1 (no spread)
N/A
N/A
N/A
0 (downspread)
1 (no spread)
CPU/PCI
Ratio
2
2
2
2
2
3
3
3
3
3
CPUCLK
Hi-Z
Reserved
Reserved
PCICLK_F
PCICLK
Hi-Z
Reserved
Reserved
Hi-Z
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
TCLK
[3]
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
REF
Hi-Z
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
TCLK
[3]
APIC
USBCLK
Hi-Z
48 MHz
48 MHz
48 MHz
48 MHz
TCLK/2
48 MHz
48 MHz
48 MHz
48 MHz
66.66 MHz 33.33 MHz
66.66 MHz 33.33 MHz
TCLK/2
Reserved
Reserved
100 MHz
100 MHz
TCLK/6
Reserved
Reserved
33.33 MHz
33.33 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
Function Table (-21S Option)
SEL100 SEL1 SEL0
0
0
0
0
0
1
1
1
1
1
0
0
1
1
1
0
0
1
1
1
0
1
0
1
1
0
1
0
1
1
SEL_SS
[2]
N/A
N/A
N/A
0 (downspread)
1 (no spread)
N/A
N/A
N/A
0 (downspread)
1 (no spread)
CPU/PCI
Ratio
2
2
2
2
2
3
3
3
3
3
CPUCLK
Hi-Z
Reserved
Reserved
PCICLK_F
PCICLK
Hi-Z
Reserved
Reserved
Hi-Z
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
TCLK
[3]
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
REF
Hi-Z
Reserved
Reserved
16.67 MHz
16.67 MHz
TCLK/12
[3]
Reserved
Reserved
16.67 MHz
16.67 MHz
APIC
USBCLK
Hi-Z
48 MHz
48 MHz
48 MHz
48 MHz
TCLK/2
48 MHz
48 MHz
48 MHz
48 MHz
66.66 MHz 33.33 MHz
66.66 MHz 33.33 MHz
TCLK/2
Reserved
Reserved
100 MHz
100 MHz
TCLK/6
Reserved
Reserved
33.33 MHz
33.33 MHz
Actual Clock Frequency Values
Clock Output
CPUCLK
CPUCLK
USBCLK
Target Frequency Actual Frequency
(MHz)
(MHz)
66.67
100
48.0
66.654
99.77
48.008
PPM
–195
–2346
167
Power Management Logic
CPU_STOP
X
0
0
1
1
PCI_STOP
X
0
1
0
1
0
1
1
1
1
PWR_DWN
CPUCLK
Low
Low
Low
Running
Running
PCICLK
Low
Low
Running
Low
Running
PCICLK_F
Low
Running
Running
Running
Running
Other
Clocks
Low
Running
Running
Running
Running
Osc.
Off
PLLs
Off
Running Running
Running Running
Running Running
Running Running
Notes:
2. Target frequency is modulated by percentage shown (max.) when SEL_SS = 0.
3. TCLK supplied on the XTALIN pin in Test Mode.
Rev 1.0, November 25, 2006
Page 3 of 11
CY2280
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Supply Voltage.................................................–0.5 to + 7.0V
Input Voltage............................................ –0.5V to V
DD
+ 0.5
Storage Temperature (Non-Condensing) ....–65 C to +150 C
Junction Temperature................................................ +150 C
Package Power Dissipation.............................................. 1W
Static Discharge Voltage .......................................... > 2000V
(per MIL-STD-883, Method 3015, like V
DD
pins tied together)
Operating Conditions
[4]
Parameter
AV
DD
, V
DDPCI
,
V
DDUSB
, V
DDREF
V
DDCPU
V
DDAPIC
T
A
C
L
Description
Analog and Digital Supply Voltage
CPU Supply Voltage
APIC Supply Voltage
Operating Temperature, Ambient
Max. Capacitive Load on
CPUCLK
PCICLK
APIC, REF
USB
Reference Frequency, Oscillator Nominal Value
Power-up time for all VDD's to reach minimum specified voltage (power
ramps must be monotonic)
14.318
0.05
Min.
3.135
2.375
2.375
0
Max.
3.465
2.625
2.625
70
20
30
20
20
14.318
50
MHz
ms
Unit
V
V
V
C
pF
f
(REF)
t
PU
Electrical Characteristics
Over the Operating Range
Parameter
V
IH
V
IL
V
OH
V
OL
V
OH
Description
High-level Input Voltage
Low-level Input Voltage
Except Crystal Inputs
[5]
Except Crystal Inputs
[5]
Test Conditions
Min. Max. Unit
2.0
0.8
I
OH
= 12 mA CPUCLK
I
OH
= 18 mA APIC
I
OL
= 12 mA
I
OL
= 18 mA
CPUCLK
APIC
2.4
V
2.0
0.4
V
V
V
V
High-level Output Voltage
[6]
V
DDCPU
= V
DDAPIC
= 2.375V
Low-level Output Voltage
[6]
V
DDCPU
= V
DDAPIC
= 2.375V
High-level Output Voltage
[6]
V
DDPCI
, AV
DD
, V
DDREF
, V
DDUSB
= 3.135V I
OH
= 14.5 mA PCICLK
I
OH
= 16 mA USBCLK
I
OH
= 16 mA REF
V
OL
Low-level Output Voltage
[6]
V
DDPCI
, AV
DD
, V
DDREF
, V
DDUSB
= 3.135V I
OL
= 9.4 mA PCICLK
I
OL
= 9 mA
I
OL
= 9 mA
USBCLK
REF
–10
–10
0.4V
V
I
IH
I
IL
I
OZ
I
DD25
I
DD25
I
DD33
I
DDS
Input High Current
Input Low Current
Output Leakage Current
Power Supply Current for
2.5V Clocks
[6]
Power Supply Current for
2.5V Clocks
[6]
Power Supply Current for
3.3V Clocks
[6]
Power-down Current
[6]
V
IH
= V
DD
V
IL
= 0V
Three-state
V
DDCPU
= 2.625V, V
IN
= 0 or V
DD
, Loaded Outputs, CPU = 66.6 MHz
V
DDCPU
= 2.625V, V
IN
= 0 or V
DD
, Loaded Outputs, CPU = 100 MHz
V
DD
= 3.465V, V
IN
= 0 or V
DD
, Loaded Outputs
Current draw in power-down state
+10
10
+10
70
100
170
500
A
A
A
mA
mA
mA
A
Notes:
4. Electrical parameters are guaranteed with these operating conditions.
5. Crystal Inputs have CMOS thresholds.
6. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Rev 1.0, November 25, 2006
Page 4 of 11
CY2280
Switching Characteristics
[6, 7]
Parameter
t
1
t
2
Output
All
CPUCLK,
APIC
PCICLK
USBCLK,
REF
CPUCLK
CPUCLK
CPUCLK
CPUCLK,
PCICLK
PCICLK,
PCICLK
CPUCLK,
APIC
APIC
CPUCLK
PCICLK
CPUCLK,
PCICLK
Description
Output Duty Cycle
[8]
CPU and APIC Clock
Rising and Falling Edge
Rate
PCI Clock Rising and
Falling Edge Rate
USB, REF Rising and
Falling Edge Rate
CPU Clock Rise Time
CPU Clock Fall Time
CPU-CPU Clock Skew
CPU-PCI Clock Skew
[9]
t
1
= t
1A
t
1B
-1,-11S,
-21S
-1,-11S,
-21S
Test Conditions
Between 0.4V and 2.0V
Min.
45
1.0
Typ.
50
Max.
55
4.0
Unit
%
V/ns
t
2
t
2
t
3
t
4
t
5
t
6
Between 0.4V and 2.4V
Between 0.4V and 2.4V
Between 0.4V and 2.0V
Between 2.0V and 0.4V
Measured at 1.25V
Measured at 1.25V for 2.5V
clocks, and at 1.5V for 3.3V
clocks
Measured at 1.5V
Measured at 1.25V for 2.5V
clocks
Measured at 1.25V
Measured at 1.25V
Measured at 1.5V
CPU, PCI clock stabilization from
power-up
1.0
0.5
4.0
2.0
1.6
1.6
100
175
4.0
V/ns
V/ns
ns
ns
ps
ns
-1,-11S,
-21S
-1,-11S,
-21S
-1,-11S,
-21S
0.4
0.4
1.5
t
7
t
8
t
9
t
10
t
11
t
12
PCI-PCI Clock Skew
CPU-APIC Clock
Skew
[10]
APIC-APIC Clock Skew
Cycle-Cycle Clock Jitter
Cycle-Cycle Clock Jitter
Power-up Time
250
-21S
2.0
100
-1,-11S,
-21S
200
250
4.5
175
250
500
3
ps
ns
ps
ps
ps
ms
Notes:
7. All parameters specified with loaded outputs.
8. Duty cycle is measured at 1.5V when V
DD
= 3.3V. When V
DD
= 2.5V, duty cycle is measured at 1.25V.
9. PCI lags CPU for -11S and -21S options.
10. APIC lags CPU for -21S option.
Rev 1.0, November 25, 2006
Page 5 of 11
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