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OXCB950-TQC60A: 产品描述Telecom IC; 产品类别无线/射频/通信电信电路; 文件大小599KB，共67页; 制造商Oxford; 官网地址http://www.oxsemi.com

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OXCB950-TQC60A概述

Telecom IC

OXCB950-TQC60A规格参数

参数名称	属性值
厂商名称	Oxford
包装说明	,
Reach Compliance Code	unknown

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EATURES

•

OXCB950

DATASHEET

Integrated High Performance UART

Cardbus / 3.3v PCI interface

DS_B005A_00

•

Arbitrary trigger levels for receiver and transmitter

FIFO interrupts and automatic in-band and out-of-

band flow control

Infra-red (IrDA) receiver and transmitter operation

9-bit data framing as well as 5,6,7 and 8

Global Interrupt Status and readable FIFO levels to

facilitate implementation of efficient device drivers

Detection of bad data in the receiver FIFO

Operation via IO or memory mapping.

2 multi-purpose I/O pins which can be configured as

interrupt input or ‘wake-up’ pins

Auto-detection of optional Microwire

EEPROM, to

reconfigure device

3.3V operation

100 pin TQFP package

•

Single high-performance UART channel

Cardbus/3.3v PCI compliant, single-function target

controller. Fully compliant to PC Card Standards,

and PCI Bus Specification 2.2, Power Management

1.0

Function access to preconfigure the UART prior to

handover to generic device drivers

UART fully software compatible with 16C550-type

devices.

Baud rates up to 15Mbps in asynchronous mode and

60Mbps in external 1x clock mode

128-byte deep FIFO per transmitter and receiver

Flexible clock prescaler from 1 to 31.875

Automated in-band flow control using programmable

Xon/Xoff in both directions

Automated out-of-band flow control using CTS#/RTS#

and/or DSR#/DTR#

ESCRIPTION

The OXCB950 is a single chip UART solution for either

cardbus or PCI-based serial add-in cards. It is a single

function device, offering memory or IO mapped access to

the ultra-high performance 950-type UART.

This UART is the fastest available PC-compatible UART,

offering data rates up to 15Mbps and 128-byte deep

transmitter and receiver FIFOs. The deep FIFOs reduce

CPU overhead and allow utilisation of higher data rates.

The UART is software compatible with the widely used

industry-standard 16C550 devices and compatibles, as

well as the OX16C95x family of high performance UARTs.

In addition to increased performance and FIFO size, the

UART also provides the full set of OX16C95x enhanced

features including automated in-band flow control, readable

FIFO levels etc.

A set of local registers is available to enhance device driver

efficiency and reduce interrupt latency. The internal UART

has features such as shadowed FIFO fill levels, an interrupt

source register and Good-Data Status, readable in one

DWORD register visible to logical function0 in IO space

and memory space.

The efficient 32-bit, 33MHz target-only interface is

compliant with both the cardbus sections of the PC CARD

Standards, and the PCI bus specifications version 2.2 and

version 1.0 of PCI Power Management Specification.

For full flexibility, all the default register values can be

overwritten using an optional Microwire

serial EEPROM.

This EEPROM can also be used to provide

function access

to pre-configure the UART into enhanced modes prior to

any cardbus/PCI configuration accesses and before control

is handed to generic device drivers.

Oxford Semiconductor Ltd.

External—Free Release

25 Milton Park, Abingdon, Oxon

OX14 4SH, UK

Tel: +44 (0)1235 824900

Fax: +44(0)1235 821141



Oxford Semiconductor 2005

OXCB950 Datasheet DS-0033 Sep 05

Part Nos. OXCB950-TQC60-A

OXCB950-TQAG

OXFORD SEMICONDUCTOR LTD.

OXCB950

ONTENTS

1.1

PERFORMANCE COMPARISON............................................................................................................ 5

IMPROVEMENTS OF THE OXCB950 OVER DISCRETE SOLUTIONS: .......................................................................... 5

6.1

6.2

6.2.1

6.3

6.3.1

6.4

6.4.1

6.4.2

6.4.3

6.4.4

6.5

6.6

6.6.1

6.6.2

6.6.3

6.7

6.8

BLOCK DIAGRAM ................................................................................................................................... 6

PIN INFORMATION.................................................................................................................................. 7

PIN DESCRIPTIONS ................................................................................................................................ 8

CONFIGURATION & OPERATION ....................................................................................................... 12

PCI TARGET CONTROLLER ................................................................................................................ 13

OPERATION ..................................................................................................................................................................... 13

CONFIGURATION SPACE ............................................................................................................................................... 14

CARDBUS / PCI CONFIGURATION SPACE REGISTER MAP ................................................................................... 14

ACCESSING THE UART FUNCTION............................................................................................................................... 16

CARDBUS/PCI ACCESS TO THE INTERNAL UART .................................................................................................. 16

ACCESSING LOCAL CONFIGURATION REGISTERS................................................................................................... 17

LOCAL CONFIGURATION AND CONTROL REGISTER ‘LCC’ (OFFSET 0X00) ........................................................ 17

MULTI-PURPOSE I/O CONFIGURATION REGISTER ‘MIC’ (OFFSET 0X04) ............................................................ 18

UART MIRROR REGISTER ‘UMR’ (OFFSET 0X08):................................................................................................... 19

GLOBAL INTERRUPT STATUS AND CONTROL REGISTER ‘GIS’ (OFFSET 0X0C) ............................................... 20

CARDBUS/ PCI INTERRUPT ........................................................................................................................................... 21

CARDBUS/PCI POWER MANAGEMENT ........................................................................................................................ 22

POWER MANAGEMENT VIA UART/ MIO PINS .......................................................................................................... 22

POWER REPORTING .................................................................................................................................................. 23

CARDBUS POWER MANAGEMENT ........................................................................................................................... 24

CARDBUS STATUS REGISTERS.................................................................................................................................... 25

CARDBUS TUPLE INFORMATION.................................................................................................................................. 27

7.1

7.1.1

7.1.2

7.1.3

7.1.4

7.1.5

7.2

7.3

7.3.1

7.3.2

7.4

7.4.1

7.5

7.5.1

7.5.2

7.5.3

7.6

7.6.1

7.6.2

7.6.3

INTERNAL 950 UART............................................................................................................................ 28

OPERATION – MODE SELECTION ................................................................................................................................. 28

450 MODE..................................................................................................................................................................... 28

550 MODE..................................................................................................................................................................... 28

750 MODE..................................................................................................................................................................... 28

650 MODE..................................................................................................................................................................... 28

950 MODE..................................................................................................................................................................... 29

REGISTER DESCRIPTION TABLES ............................................................................................................................... 30

RESET CONFIGURATION ............................................................................................................................................... 34

HARDWARE RESET .................................................................................................................................................... 34

SOFTWARE RESET ..................................................................................................................................................... 34

TRANSMITTER AND RECEIVER FIFOS ......................................................................................................................... 35

FIFO CONTROL REGISTER ‘FCR’ .............................................................................................................................. 35

LINE CONTROL & STATUS............................................................................................................................................. 36

FALSE START BIT DETECTION.................................................................................................................................. 36

LINE CONTROL REGISTER ‘LCR’............................................................................................................................... 36

LINE STATUS REGISTER ‘LSR’ .................................................................................................................................. 37

INTERRUPTS & SLEEP MODE........................................................................................................................................ 38

INTERRUPT ENABLE REGISTER ‘IER’....................................................................................................................... 38

INTERRUPT STATUS REGISTER ‘ISR’....................................................................................................................... 39

INTERRUPT DESCRIPTION ........................................................................................................................................ 39

External-Free Release

Page 2

DS-0033 Sep 05

OXFORD SEMICONDUCTOR LTD.

OXCB950

7.6.4

SLEEP MODE ............................................................................................................................................................... 40

7.7

MODEM INTERFACE ....................................................................................................................................................... 40

7.7.1

MODEM CONTROL REGISTER ‘MCR’........................................................................................................................ 40

7.7.2

MODEM STATUS REGISTER ‘MSR’ ........................................................................................................................... 41

7.8

OTHER STANDARD REGISTERS ................................................................................................................................... 41

7.8.1

DIVISOR LATCH REGISTERS ‘DLL & DLM’................................................................................................................ 41

7.8.2

SCRATCH PAD REGISTER ‘SPR’ ............................................................................................................................... 41

7.9

AUTOMATIC FLOW CONTROL....................................................................................................................................... 42

7.9.1

ENHANCED FEATURES REGISTER ‘EFR’................................................................................................................. 42

7.9.2

SPECIAL CHARACTER DETECTION .......................................................................................................................... 43

7.9.3

AUTOMATIC IN-BAND FLOW CONTROL ................................................................................................................... 43

7.9.4

AUTOMATIC OUT-OF-BAND FLOW CONTROL ......................................................................................................... 43

7.10 BAUD RATE GENERATION............................................................................................................................................. 44

7.10.1

GENERAL OPERATION ............................................................................................................................................... 44

7.10.2

CLOCK PRESCALER REGISTER ‘CPR’...................................................................................................................... 44

7.10.3

TIMES CLOCK REGISTER ‘TCR’................................................................................................................................. 44

7.10.4

EXTERNAL 1X CLOCK MODE..................................................................................................................................... 46

7.10.5

CRYSTAL OSCILLATOR CIRCUIT .............................................................................................................................. 46

7.11 ADDITIONAL FEATURES ................................................................................................................................................ 46

7.11.1

ADDITIONAL STATUS REGISTER ‘ASR’ .................................................................................................................... 46

7.11.2

FIFO FILL LEVELS ‘TFL & RFL’ ................................................................................................................................... 47

7.11.3

ADDITIONAL CONTROL REGISTER ‘ACR’................................................................................................................. 47

7.11.4

TRANSMITTER TRIGGER LEVEL ‘TTL’ ...................................................................................................................... 48

7.11.5

RECEIVER INTERRUPT. TRIGGER LEVEL ‘RTL’ ...................................................................................................... 48

7.11.6

FLOW CONTROL LEVELS ‘FCL’ & ‘FCH’ .................................................................................................................... 48

7.11.7

DEVICE IDENTIFICATION REGISTERS...................................................................................................................... 49

7.11.8

CLOCK SELECT REGISTER ‘CKS’.............................................................................................................................. 49

7.11.9

NINE-BIT MODE REGISTER ‘NMR’ ............................................................................................................................. 49

7.11.10 MODEM DISABLE MASK ‘MDM’ .................................................................................................................................. 50

7.11.11 READABLE FCR ‘RFC’................................................................................................................................................. 50

7.11.12 GOOD-DATA STATUS REGISTER ‘GDS’.................................................................................................................... 51

7.11.13 DMA STATUS REGISTER ‘DMS’ ................................................................................................................................. 51

7.11.14 PORT INDEX REGISTER ‘PIX’..................................................................................................................................... 51

7.11.15 CLOCK ALTERATION REGISTER ‘CKA’ ..................................................................................................................... 51

8.1

8.1.1

8.1.2

8.1.3

8.1.4

8.1.5

8.1.6

SERIAL EEPROM SPECIFICATION ..................................................................................................... 52

EEPROM DATA ORGANISATION ................................................................................................................................... 52

ZONE0: HEADER ......................................................................................................................................................... 52

ZONE1 : POWER MANAGEMENT DATA AND DATA_SCALE ZONE ...................................................................... 53

ZONE2: LOCAL CONFIGURATION REGISTER ZONE ............................................................................................... 53

ZONE 3 : CARDBUS INFORMATION STRUCTURE ................................................................................................... 53

ZONE4: PCI CONFIGURATION REGISTERS ............................................................................................................. 54

ZONE5: FUNCTION ACCESS ...................................................................................................................................... 54

11.1

11.2

COMPLIANCE TO PC CARD STANDARDS, 7.0 AND 7.1 .................................................................. 56

OPERATING CONDITIONS ............................................................................................................... 59

DC ELECTRICAL CHARACTERISTICS............................................................................................ 60

NORMAL 3.3V I/O BUFFERS........................................................................................................................................... 60

5.0V TOLERANT I/O BUFFERS ...................................................................................................................................... 60

12.1

AC ELECTRICAL CHARACTERISTICS............................................................................................ 61

DUAL MODE (CARDBUS/PCI) I/O BUFFERS................................................................................................................ 61

13.1

13.2

POWER CONSUMPTION MEASUREMENTS................................................................................... 62

STATIC CURRENT CONSUMPTION ............................................................................................................................... 62

CURRENT CONSUMPTION IN APPLICATION ............................................................................................................... 62

External-Free Release

Page 3

DS-0033 Sep 05

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器件捷径: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

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