Preliminary
GS842Z18/36AB-200/180/166/150/100
119-Bump BGA
Commercial Temp
Industrial Temp
Features
• 256K x 18 and 128K x 36 configurations
• User configurable Pipeline and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization
• Fully pin compatible with both pipelined and flow through
NtRAM™, NoBL™ and ZBT™ SRAMs
• Pin-compatible with 2M, 8M, and 16M devices
• 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleave Burst mode
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• Clock Control, registered address, data, and control
• ZZ Pin for automatic power-down
• JEDEC-standard 119-bump BGA package
–200
–180
–166
–150
–100
tCycle 5.0 ns 5.5 ns 6.0 ns 6.6 ns
10 ns
Pipeline
t
KQ
3.0 ns 3.2 ns 3.5 ns 3.8 ns
4.5 ns
3-1-1-1
I
DD
370 mA 335 mA 310 mA 280 mA 190 mA
Flow
t
KQ
7.5 ns
8 ns
8.5 ns
10 ns
12 ns
Through
tCycle 8.8 ns 9.1 ns 10 ns
12 ns
15 ns
2-1-1-1
I
DD
220 mA 210 mA 190 mA 165 mA 135 mA
4Mb Pipelined and Flow Through
200 MHz–100 MHz
3.3 V V
DD
Synchronous NBT SRAMs
2.5 V and 3.3 V V
DDQ
Functional Description
The GS842Z18/36AB is a 4Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS842Z18/36AT may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS842Z18/36AT is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 119-bump BGA package.
Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles
Clock
Address
Read/Write
A
R
B
W
Q
A
C
R
D
B
Q
A
D
W
Q
C
D
B
E
R
D
D
Q
C
F
W
Q
E
D
D
Q
E
Flow Through
Data I/O
Pipelined
Data I/O
Rev: 1.01 3/2002
1/33
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
Preliminary
GS842Z18/36AB-200/180/166/150/100
GS842Z18A Pad Out
119 Bump BGA—Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQ
B1
NC
V
DDQ
NC
DQ
B4
V
DDQ
NC
DQ
B6
V
DDQ
DQ
B8
NC
NC
NC
V
DDQ
2
A
6
E
2
A
5
NC
DQ
B2
NC
DQ
B3
NC
V
DD
DQ
B5
NC
DQ
B7
NC
DQ
B9
A
2
A
10
TMS
3
A
7
A
4
A
3
V
SS
V
SS
V
SS
B
B
V
SS
NC
V
SS
NC
V
SS
V
SS
V
SS
LBO
A
11
TDI
4
NC
ADV
V
DD
ZQ
E
1
G
NC
W
V
DD
CK
NC
CKE
A
1
A
0
V
DD
NC
TCK
5
A
8
A
15
A
14
V
SS
V
SS
V
SS
NC
V
SS
NC
V
SS
B
A
V
SS
V
SS
V
SS
FT
A
12
TDO
6
A
9
E
3
A
16
DQ
A9
NC
DQ
A7
NC
DQ
A5
V
DD
NC
DQ
A3
NC
DQ
A2
NC
A
13
A
17
NC
7
V
DDQ
NC
NC
NC
DQ
A8
V
DDQ
DQ
A6
NC
V
DDQ
DQ
A4
NC
V
DDQ
NC
DQ
A1
NC
ZZ
V
DDQ
Rev: 1.01 3/2002
2/33
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS842Z18/36AB-200/180/166/150/100
GS842Z36A Pad Out
119 Bump BGA—Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQ
C4
DQ
C3
V
DDQ
DQ
C2
DQ
C1
V
DDQ
DQ
D1
DQ
D2
V
DDQ
DQ
D3
DQ
D4
NC
NC
V
DDQ
2
A
6
E
2
A
5
DQ
C9
DQ
C8
DQ
C7
DQ
C6
DQ
C5
V
DD
DQ
D5
DQ
D6
DQ
D7
DQ
D8
DQ
D9
A
2
NC
TMS
3
A
7
A
4
A
3
V
SS
V
SS
V
SS
B
C
V
SS
NC
V
SS
B
D
V
SS
V
SS
V
SS
LBO
A
10
TDI
4
NC
ADV
V
DD
ZQ
E
1
G
NC
W
V
DD
CK
NC
CKE
A
1
A
0
V
DD
A
11
TCK
5
A
8
A
15
A
14
V
SS
V
SS
V
SS
B
B
V
SS
NC
V
SS
B
A
V
SS
V
SS
V
SS
FT
A
12
TDO
6
A
9
E
3
A
16
DQ
B9
DQ
B8
DQ
B7
DQ
B6
DQ
B5
V
DD
DQ
A5
DQ
A6
DQ
A7
DQ
A8
DQ
A9
A
13
NC
NC
7
V
DDQ
NC
NC
DQ
B4
DQ
B3
V
DDQ
DQ
B2
DQ
B1
V
DDQ
DQ
A1
DQ
A2
V
DDQ
DQ
A3
DQ
A4
NC
ZZ
V
DDQ
Rev: 1.01 3/2002
3/33
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS842Z18/36AB-200/180/166/150/100
GS842Z18/36A Pin Description
Pin Location
P4, N4
A2, A3, A5, A6, B3, B5, C2, C3, C5,
C6, R2, R6, T3, T5
T4
A4, T2, T6
T2, T6
K7, L7, N7, P7, K6, L6, M6, N6, P6
H7, G7, E7, D7, H6, G6, F6, E6, D6
H1, G1, E1, D1, H2, G2, F2, E2, D2
K1, L1, N1, P1, K2, L2, M2, N2, P2
L5, G5, G3, L3
P7, N6, L6, K7, H6, G7, F6, E7, D6
D1, E2, G2, H1, K2, L1, M2, N1, P2
L5, G3
P6, N7, M6, L7, K6, H7, G6, E6, D7,
D2, E1, F2, G1, H2, K1, L2, N2, P1,
G5, L3, T4, A4
K4
M4
H4
E4, B6
B2
F4
B4
T7
R5
R3
D4
B1, C1, R1, T1, L4, B7, C7, U6, J3,
J5, G4, R7
U2
Symbol
A
0
, A
1
An
An
NC
An
DQ
A1
–DQ
A9
DQ
B
1
–DQ
B
9
DQ
C1
–DQ
C
9
DQ
D
1
–DQ
D
9
B
A
, B
B
, B
C
, B
D
DQ
A1
–DQ
A9
DQ
B
1
–DQ
B
9
B
A
, B
B
NC
CK
CKE
W
E
1
, E
3
E
2
G
ADV
ZZ
FT
LBO
ZQ
NC
TMS
Type
I
I
I
—
I
I/O
I
I/O
I
—
I
I
I
I
I
I
I
I
I
I
I
—
I
Description
Address field LSBs and Address Counter Preset Inputs
Address Inputs
Address Inputs (x36 Version)
No Connect (x36 Version)
Address Inputs (x18 Version)
Data Input and Output pins (x36 Version)
Byte Write Enable for DQ
A
, DQ
B
, DQ
C
, DQ
A
I/Os; active low ( x36 Version)
Data Input and Output pin (x18 Version)
Byte Write Enable for DQ
A
, DQ
B
Data I/Os; active low ( x18 Version)
No Connect (x18 Version)
Clock Input Signal; active high
Clock Input Buffer Enable; active low
Write Enable. Writes all enabled bytes; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Burst address counter advance enable; active high
Sleep Mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
FLXDrive Output Impedance Control
(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])
No Connect
Scan Test Mode Select
Rev: 1.01 3/2002
4/33
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS842Z18/36AB-200/180/166/150/100
GS842Z18/36A Pin Description
Pin Location
U3
U5
U4
J2, C4, J4, R4, J6
D3, E3, F3, H3, K3, M3, N3, P3, D5,
E5, F5, H5, K5, M5, N5, P5
A1, F1, J1, M1, U1, A7, F7,
J7, M7, U7
K4
Symbol
TDI
TDO
TCK
V
DD
V
SS
V
DDQ
CK
Type
I
O
I
I
I
I
I
Description
Scan Test Data In
Scan Test Data Out
Scan Test Clock
Core power supply
I/O and Core Ground
Output driver power supply
Clock Input Signal; active high
Functional Details
Clocking
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipelined Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E
1
, E
2,
and E
3
). Deassertion of any one of the Enable
inputs will deactivate the device.
Function
Read
Write Byte “a”
Write Byte “b”
Write Byte “c”
Write Byte “d”
Write all Bytes
Write Abort/NOP
W
H
L
L
L
L
L
L
B
A
X
L
H
H
H
L
H
B
B
X
H
L
H
H
L
H
B
C
X
H
H
L
H
L
H
B
D
X
H
H
H
L
L
H
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three
chip enables (E1, E2, and E3) are active, the write enable input signal W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the Output pins.
Write operation occurs when the RAM is selected, CKE is active and the write input is sampled low at the rising edge of clock. The
Byte Write Enable inputs (B
A
, B
B
, B
C,
and B
D
) determine which bytes will be written. All or none may be activated. A write cycle
Rev: 1.01 3/2002
5/33
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
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