SN54HC00, SN74HC00
QUADRUPLE 2 INPUT POSITIVE NAND GATES
SCLS181E − DECEMBER 1982 − REVISED AUGUST 2003
D
Wide Operating Voltage Range of 2 V to 6 V
D
Outputs Can Drive Up To 10 LSTTL Loads
D
Low Power Consumption, 20-µA Max I
CC
SN54HC00 . . . J OR W PACKAGE
SN74HC00 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
D
Typical t
pd
= 8 ns
D
±4-mA
Output Drive at 5 V
D
Low Input Current of 1
µA
Max
SN54HC00 . . . FK PACKAGE
(TOP VIEW)
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
4B
4A
4Y
3B
3A
3Y
1Y
NC
2A
NC
2B
1B
1A
NC
V
CC
4B
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
4A
NC
4Y
NC
3B
NC − No internal connection
description/ordering information
The ’HC00 devices contain four independent 2-input NAND gates. They perform the Boolean function
Y = A
•
B or Y = A + B in positive logic.
ORDERING INFORMATION
TA
PDIP − N
PACKAGE†
Tube of 25
Tube of 50
SOIC − D
−40 C 85°C
−40°C to 85 C
SOP − NS
SSOP − DB
Reel of 2500
Reel of 250
Reel of 2000
Reel of 2000
Tube of 90
TSSOP − PW
CDIP − J
−55 C 125°C
−55°C to 125 C
CFP − W
LCCC − FK
Reel of 2000
Reel of 250
Tube of 25
Tube of 150
Tube of 55
ORDERABLE
PART NUMBER
SN74HC00N
SN74HC00D
SN74HC00DR
SN74HC00DT
SN74HC00NSR
SN74HC00DBR
SN74HC00PW
SN74HC00PWR
SN74HC00PWT
SNJ54HC00J
SNJ54HC00W
SNJ54HC00FK
SNJ54HC00J
SNJ54HC00W
SNJ54HC00FK
HC00
HC00
HC00
HC00
TOP-SIDE
MARKING
SN74HC00N
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
2Y
GND
NC
3Y
3A
On products compliant to MIL PRF 38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
Copyright
2003, Texas Instruments Incorporated
1
SN54HC00, SN74HC00
QUADRUPLE 2 INPUT POSITIVE NAND GATES
SCLS181E − DECEMBER 1982 − REVISED AUGUST 2003
FUNCTION TABLE
(each gate)
INPUTS
A
H
L
X
B
H
X
L
OUTPUT
Y
L
H
H
logic diagram (positive logic)
A
B
Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Continuous output current, I
O
(V
O
= 0 to V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±25
mA
Continuous current through V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±50
mA
Package thermal impedance,
θ
JA
(see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HC00
MIN
VCC
VIH
Supply voltage
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
VCC = 2 V
VIL
VI
VO
∆t/∆v
Low-level input voltage
Input voltage
Output voltage
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
VCC = 4.5 V
VCC = 6 V
0
0
2
1.5
3.15
4.2
0.5
1.35
1.8
VCC
VCC
1000
500
400
0
0
NOM
5
MAX
6
SN74HC00
MIN
2
1.5
3.15
4.2
0.5
1.35
1.8
VCC
VCC
1000
500
400
ns
V
V
V
V
NOM
5
MAX
6
UNIT
V
High-level input voltage
Input transition rise/fall time
TA
Operating free-air temperature
−55
125
−40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN54HC00, SN74HC00
QUADRUPLE 2 INPUT POSITIVE NAND GATES
SCLS181E − DECEMBER 1982 − REVISED AUGUST 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
2V
IOH = −20
µA
VOH
VI = VIH or VIL
IOH = −4 mA
IOH = −5.2 mA
IOL = 20
µA
VOL
VI = VIH or VIL
IOL = 4 mA
IOL = 5.2 mA
II
ICC
Ci
VI = VCC or 0
VI = VCC or 0,
IO = 0
4.5 V
6V
4.5 V
6V
2V
4.5 V
6V
4.5 V
6V
6V
6V
2 V to 6 V
3
TA = 25°C
MIN
TYP
MAX
1.9
4.4
5.9
3.98
5.48
1.998
4.499
5.999
4.3
5.8
0.002
0.001
0.001
0.17
0.15
±0.1
0.1
0.1
0.1
0.26
0.26
±100
2
10
SN54HC00
MIN
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±1000
40
10
MAX
SN74HC00
MIN
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±1000
20
10
nA
µA
pF
V
V
MAX
UNIT
switching characteristics over recommended operating free-air temperature range, C
L
= 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
2V
tpd
A or B
Y
4.5 V
6V
2V
tt
Y
4.5 V
6V
TA = 25°C
MIN
TYP
MAX
45
9
8
38
8
6
90
18
15
75
15
13
SN54HC00
MIN
MAX
135
27
23
110
22
19
SN74HC00
MIN
MAX
115
23
20
95
19
16
ns
ns
UNIT
operating characteristics, T
A
= 25°C
PARAMETER
Cpd
Power dissipation capacitance per gate
TEST CONDITIONS
No load
TYP
20
UNIT
pF
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3
SN54HC00, SN74HC00
QUADRUPLE 2 INPUT POSITIVE NAND GATES
SCLS181E − DECEMBER 1982 − REVISED AUGUST 2003
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
Test
Point
CL = 50 pF
(see Note A)
In-Phase
Output
Input
VCC
50%
tPLH
50%
10%
tPHL
Out-of-Phase
Output
90%
50%
10%
tf
90%
tr
Input
50%
10%
90%
90%
VCC
50%
10% 0 V
tf
tPLH
50%
10%
90%
tr
50%
0V
tPHL
90%
VOH
50%
10%
VOL
tf
VOH
VOL
LOAD CIRCUIT
tr
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR
≤
1 MHz, ZO = 50
Ω,
tr = 6 ns, tf = 6 ns.
C. The outputs are measured one at a time with one input transition per measurement.
D. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
4-Dec-2014
PACKAGING INFORMATION
Orderable Device
5962-8403701VCA
Status
(1)
Package Type Package Pins Package
Drawing
Qty
CDIP
J
14
1
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C)
-55 to 125
Device Marking
(4/5)
Samples
ACTIVE
TBD
A42
N / A for Pkg Type
5962-8403701VC
A
SNV54HC00J
5962-8403701VD
A
SNV54HC00W
84037012A
SNJ54HC
00FK
8403701CA
SNJ54HC00J
8403701DA
SNJ54HC00W
JM38510/
65001B2A
JM38510/
65001BCA
JM38510/
65001BDA
JM38510/
65001B2A
JM38510/
65001BCA
JM38510/
65001BDA
SN54HC00J
HC00
HC00
HC00
HC00
5962-8403701VDA
ACTIVE
CFP
W
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
84037012A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
8403701CA
8403701DA
JM38510/65001B2A
JM38510/65001BCA
JM38510/65001BDA
M38510/65001B2A
M38510/65001BCA
M38510/65001BDA
SN54HC00J
SN74HC00D
SN74HC00DBR
SN74HC00DE4
SN74HC00DG4
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
CDIP
CFP
LCCC
CDIP
CFP
LCCC
CDIP
CFP
CDIP
SOIC
SSOP
SOIC
SOIC
J
W
FK
J
W
FK
J
W
J
D
DB
D
D
14
14
20
14
14
20
14
14
14
14
14
14
14
1
1
1
1
1
1
1
1
1
50
2000
50
50
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
A42
A42
POST-PLATE
A42
A42
POST-PLATE
A42
A42
A42
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Addendum-Page 1
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