Preliminary
GS8170D18/36B-333/300/250
209-Bump BGA
Commercial Temp
Industrial Temp
18Mb
Σ
1x2Lp DDR SRAM
1M x 18, 512K x 36
250 - 333 MHz
1.8 V V
DD
1.8 V and 1.5 V I/O
Features
• Double Data Rate Read and Write mode
• JEDEC standard SigmaRAM
™
pinout and package
• 1.8 V +150/–100 mV core power supply
• 1.5 V or 1.8 V I/O supply
• Pipelined read operation.
• Fully coherent read and write pipelines
• Echo Clock outputs track data output drivers
• ZQ mode pin for user-selectable output drive strength
• 2 User programmable chip enable inputs for easy depth
expansion.
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package
• Pin compatible with future 32M, 64M, and 128M devices
SigmaRAM Family Overview
GS8170D18/36 SigmaRAMs are built in compliance with the
SigmaRAM pinout standard for synchronous SRAMs.
18,874,368-bit (18Mb) SRAMs. These are the first in a family
of wide, very low voltage CMOS I/O SRAMs designed to
operate at the speeds needed to implement economical high
performance networking systems.
GSI's
ΣRAMs
are offered in a number of configurations that
emulate other synchronous SRAMs, such as Burst RAMs,
NBT, Late Write, or Double Data Rate (DDR) SRAMs. The
logical differences between the protocols employed by these
RAMs hinge mainly on various combinations of address
bursting, output data registering and write cueing. The
ΣRAM
™
family standard allows a user to implement the
interface protocol best suited to the task at hand.
Bottom View
209-Bump, 14 mm x 22 mm BGA
1 mm Bump Pitch, 11 x 19 Bump Array
Because the DDR
ΣRAM
always transfers data in two halves,
A0 is internally set to 0 for the first half of each read or write
transfer, and automatically incremented to 1 for the falling
edge transfer. The address field of a DDR
ΣRAM
is always one
address pin less than the advertised index depth (e.g., the 1M x
18 has a 512k addressable index).
In Pipeline mode, single data rate
ΣRAMs
incorporate a rising-
edge-triggered output register. In DDR mode, rising- and
falling-edge-triggered output registers are employed. For read
cycles, a DDR SRAM’s output data is staged at the input of an
edge-triggered output register during the access cycle and then
released to the output drivers at the next rising and subsequent
falling edge of clock.
GS817x18/36/72B
ΣRAMs
are implemented with GSI's high
performance CMOS technology and are packaged in a 209-
bump BGA.
Functional Description
Because SigmaRAMs are synchronous devices, address, and
read/write control inputs are captured on the rising edge of the
input clock. Write cycles are internally self-timed and initiated
by the rising edge of the clock input. This feature eliminates
complex off-chip write pulse generation required by
asynchronous SRAMs and simplifies input signal timing. In
DDR mode the device captures Data In on both rising and
falling edges of clock and drives data on both clock edges as
well.
Rev: 1.04b 06/2001
1/32
© 2001, GSI Technology, Inc.
D
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
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