SN54HC20, SN74HC20
DUAL 4-INPUT POSITIVE-NAND GATES
SCLS086D – DECEMBER 1982 – REVISED FEBRUARY 2000
D
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW), and
Ceramic Flat (W) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) DIPs
SN54HC20 . . . J OR W PACKAGE
SN74HC20 . . . D, DB, N, OR PW PACKAGE
(TOP VIEW)
description
The ’HC20 devices contain two independent
4-input NAND gates. They perform the Boolean
function Y = A
•
B
•
C
•
D or Y = A + B + C + D in
positive logic.
The SN54HC20 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74HC20 is characterized for
operation from –40°C to 85°C.
FUNCTION TABLE
(each gate)
INPUTS
A
H
L
X
X
X
B
H
X
L
X
X
C
H
X
X
L
X
D
H
X
X
X
L
OUTPUT
Y
L
H
H
H
H
1A
1B
NC
1C
1D
1Y
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
2D
2C
NC
2B
2A
2Y
SN54HC20 . . . FK PACKAGE
(TOP VIEW)
1B
1A
NC
V
CC
2D
NC
NC
1C
NC
1D
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
2C
NC
NC
NC
2B
NC – No internal connection
logic symbol
†
1A
1B
1C
1D
2A
2B
2C
2D
1
2
4
5
9
10
12
13
8
2Y
&
6
1Y
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, N, PW, and W packages.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
©
2000, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1Y
GND
NC
2Y
2A
1
SN54HC20, SN74HC20
DUAL 4-INPUT POSITIVE-NAND GATES
SCLS086D – DECEMBER 1982 – REVISED FEBRUARY 2000
logic diagram (positive logic)
1A
1B
1C
1D
1
2
4
5
6
1Y
2A
2B
2C
2D
9
10
12
13
8
2Y
Pin numbers shown are for the D, DB, J, N, PW, and W packages.
absolute maximum ratings over operating free-air temperature range
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Continuous output current, I
O
(V
O
= 0 to V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±25
mA
Continuous current through V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±50
mA
Package thermal impedance,
θ
JA
(see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 3)
SN54HC20
MIN
VCC
VIH
Supply voltage
High-level input voltage
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
VCC = 2 V
VIL
VI
VO
tt
Low-level input voltage
Input voltage
Output voltage
Input transition (rise and fall) time
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
VCC = 4.5 V
VCC = 6 V
2
1.5
3.15
4.2
0
0
0
0
0
0
0
0
0.5
1.35
1.8
VCC
VCC
1000
500
400
NOM
5
MAX
6
SN74HC20
MIN
2
1.5
3.15
4.2
0
0
0
0
0
0
0
0
0.5
1.35
1.8
VCC
VCC
1000
500
400
ns
V
V
V
V
NOM
5
MAX
6
UNIT
V
TA
Operating free-air temperature
–55
125
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
2
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SN54HC20, SN74HC20
DUAL 4-INPUT POSITIVE-NAND GATES
SCLS086D – DECEMBER 1982 – REVISED FEBRUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
2V
IOH = –20
µA
VOH
VI = VIH or VIL
IOH = –4 mA
IOH = –5.2 mA
IOL = 20
µA
VOL
VI = VIH or VIL
IOL = 4 mA
IOL = 5.2 mA
II
ICC
Ci
VI = VCC or 0
VI = VCC or 0,
IO = 0
4.5 V
6V
4.5 V
6V
2V
4.5 V
6V
4.5 V
6V
6V
6V
2 V to 6 V
3
TA = 25°C
MIN
TYP
MAX
1.9
4.4
5.9
3.98
5.48
1.998
4.499
5.999
4.3
5.8
0.002
0.001
0.001
0.17
0.15
±0.1
0.1
0.1
0.1
0.26
0.26
±100
2
10
SN54HC20
MIN
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±1000
40
10
MAX
SN74HC20
MIN
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±1000
20
10
nA
µA
pF
V
V
MAX
UNIT
switching characteristics over recommended operating free-air temperature range, C
L
= 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
2V
tpd
A, B, C, or D
Y
4.5 V
6V
2V
tt
Y
4.5 V
6V
TA = 25°C
MIN
TYP
MAX
45
14
11
27
9
7
110
22
19
75
15
13
SN54HC20
MIN
MAX
165
33
28
110
22
19
SN74HC20
MIN
MAX
140
28
24
95
19
16
ns
ns
UNIT
operating characteristics, T
A
= 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
No load
TYP
25
UNIT
pF
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3
SN54HC20, SN74HC20
DUAL 4-INPUT POSITIVE-NAND GATES
SCLS086D – DECEMBER 1982 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
Test
Point
CL = 50 pF
(see Note A)
In-Phase
Output
Input
VCC
50%
tPLH
50%
10%
tPHL
Out-of-Phase
Output
90%
50%
10%
tf
90%
tr
Input
50%
10%
90%
90%
VCC
50%
10% 0 V
tf
tPLH
50%
10%
90%
tr
50%
0V
tPHL
90%
VOH
50%
10%
VOL
tf
VOH
VOL
LOAD CIRCUIT
tr
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR
≤
1 MHz, ZO = 50
Ω,
tr = 6 ns, tf = 6 ns.
C. The outputs are measured one at a time with one input transition per measurement.
D. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
4
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
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Copyright
©
2000, Texas Instruments Incorporated
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