MOTOROLA
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
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by MCM63P737K/D
Advance Information
128K x 36 and 256K x 18 Bit
Pipelined BurstRAM
Synchronous Fast Static RAM
The MCM63P737K and MCM63P819K are 4M–bit synchronous fast static
RAMs designed to provide a burstable, high performance, secondary cache. The
MCM63P737K (organized as 128K words by 36 bits) and the MCM63P819K
(organized as 256K words by 18 bits) integrate input registers, an output register,
a 2–bit address counter, and high speed SRAM onto a single monolithic circuit
for reduced parts count in cache data RAM applications. Synchronous design
allows precise cycle control with the use of an external clock (K).
Addresses (SA), data inputs (DQx), and all control signals except output
enable (G), sleep mode (ZZ), and linear burst order (LBO) are clock (K)
controlled through positive–edge–triggered noninverting registers.
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst
addresses can be generated internally by the MCM63P737K and MCM63P819K
(burst sequence operates in linear or interleaved mode dependent upon the state
of LBO) and controlled by the burst address advance (ADV) input pin.
Write cycles are internally self–timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.
Synchronous byte write (SBx), synchronous global write (SGW), and synchro-
nous write enable (SW) are provided to allow writes to either individual bytes or
to all bytes. The bytes are designated as “a”, “b”, etc. SBa controls DQa, SBb
controls DQb, etc. Individual bytes are written if the selected byte writes SBx are
asserted with SW. All bytes are written if either SGW is asserted or if all SBx and
SW are asserted.
For read cycles, pipelined SRAMs output data is temporarily stored by an
edge–triggered output register and then released to the output buffers at the next
rising edge of clock (K).
The MCM63P737K and MCM63P819K operate from a 3.3 V core power
supply and all outputs operate on a 2.5 V or 3.3 V power supply. All inputs and
outputs are JEDEC standard JESD8–5 compatible.
•
MCM63P737K / MCM63P819K–166 = 3.5 ns Access / 6 ns Cycle (166 MHz)
MCM63P737K / MCM63P819K–150 = 3.8 ns Access / 6.7 ns Cycle (150 MHz)
MCM63P737K / MCM63P819K–133 = 4 ns Access / 7.5 ns Cycle (133 MHz)
•
3.3 V +10%, –5% Core Power Supply, 2.5 V or 3.3 V I/O Supply
•
ADSP, ADSC, and ADV Burst Control Pins
•
Selectable Burst Sequencing Order (Linear/Interleaved)
•
Single–Cycle Deselect Timing
•
Internally Self–Timed Write Cycle
•
Byte Write and Global Write Control
•
Sleep Mode (ZZ)
•
JEDEC Standard 100–Pin TQFP and 119–Pin PBGA Packages
MCM63P737K
MCM63P819K
TQ PACKAGE
TQFP
CASE 983A–01
Freescale Semiconductor, Inc...
ZP PACKAGE
PBGA
CASE 999–02
This document contains information on a new product. Specifications and information herein are subject to change without notice.
REV 1
1/24/00
©
Motorola, Inc. 2000
MOTOROLA FAST SRAM
For More Information On This Product,
Go to: www.freescale.com
MCM63P737K•MCM63P819K
1
Freescale Semiconductor, Inc.
FUNCTIONAL BLOCK DIAGRAM
LBO
ADV
K
ADSC
ADSP
K2
BURST
COUNTER
CLR
2
2
17/18
128K x 36 / 256K x 18
ARRAY
SA
SA1
SA0
ADDRESS
REGISTER
17/18
15/16
SGW
SW
WRITE
REGISTER
a
36/18
36/18
Freescale Semiconductor, Inc...
SBa
SBb
WRITE
REGISTER
b
4/2
WRITE
REGISTER
c*
DATA–IN
REGISTER
K
DATA–OUT
REGISTER
SBc*
SBd*
WRITE
REGISTER
d*
K2
K
SE1
SE2
SE3
G
ZZ
* Valid only for MCM63P737K.
ENABLE
REGISTER
ENABLE
REGISTER
DQa – DQd/
DQa–DQb
MCM63P737K•MCM63P819K
2
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Go to: www.freescale.com
MOTOROLA FAST SRAM
Freescale Semiconductor, Inc.
MCM63P737K PIN ASSIGNMENTS
SA
SA
SE1
SE2
SBd
SBc
SBb
SBa
SE3
VDD
VSS
K
SGW
SW
G
ADSC
ADSP
ADV
SA
SA
1
DQb
DQb
DQb
VDDQ
VSS
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
DQa
A
B
C
D
E
DQc
F
G
DQc
H
J
K
L
DQd
M
DQc
VDDQ
VDDQ
NC
NC
DQc
2
SA
SE2
SA
DQc
DQc
DQc
DQc
DQc
3
SA
SA
SA
VSS
VSS
VSS
SBc
VSS
NC
VSS
SBd
VSS
VSS
VSS
LBO
SA
NC
4
ADSP
ADSC
VDD
NC
SE1
G
ADV
SGW
VDD
K
NC
SW
SA1
SA0
VDD
SA
NC
5
SA
SA
SA
VSS
VSS
VSS
SBb
VSS
NC
VSS
SBa
VSS
VSS
VSS
NC
SA
NC
6
7
Freescale Semiconductor, Inc...
DQc
DQc
DQc
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQd
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
1
79
2
78
3
77
4
76
5
75
6
74
7
73
8
72
9
71
10
70
11
69
12
68
13
67
14
66
15
65
16
64
17
63
18
62
19
61
20
60
21
59
22
58
23
57
24
56
25
55
26
54
27
53
28
52
29
51
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
LBO
SA
SA
SA
SA
SA1
SA0
NC
NC
VSS
VDD
NC
NC
SA
SA
SA
SA
SA
SA
SA
SA VDDQ
SE3
SA
DQb
DQb
NC
NC
DQb
DQb
DQb VDDQ
DQb
DQb
DQb
DQb
VDDQ VDD
DQd
DQd
DQd
VDD VDDQ
DQa
DQa
DQa
DQa
VDDQ DQd
N
P
R
T
NC
U
VDDQ
NC
NC
DQd
DQd
NC
DQd
DQd
SA
DQa VDDQ
DQa
DQa
SA
NC
NC
DQa
DQa
NC
ZZ
VDDQ
100–PIN TQFP
TOP VIEW
119–BUMP PBGA
TOP VIEW
Not to Scale
MOTOROLA FAST SRAM
For More Information On This Product,
Go to: www.freescale.com
MCM63P737K•MCM63P819K
3
Freescale Semiconductor, Inc.
MCM63P737K TQFP PIN DESCRIPTIONS
Pin Locations
85
Symbol
ADSC
Type
Input
Description
Synchronous Address Status Controller: Active low, interrupts any
ongoing burst and latches a new external address. Used to initiate a
READ, WRITE, or chip deselect.
Synchronous Address Status Processor: Active low, interrupts any
ongoing burst and latches a new external address. Used to initiate a
new READ, WRITE, or chip deselect (exception — chip deselect does
not occur when ADSP is asserted and SE1 is high).
Synchronous Address Advance: Increments address count in
accordance with counter type selected (linear/interleaved).
Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b, c, d).
84
ADSP
Input
83
(a) 51, 52, 53, 56, 57, 58, 59, 62, 63
(b) 68, 69, 72, 73, 74, 75, 78, 79, 80
(c) 1, 2, 3, 6, 7, 8, 9, 12, 13
(d) 18, 19, 22, 23, 24, 25, 28, 29, 30
86
ADV
DQx
Input
I/O
G
Input
Freescale Semiconductor, Inc...
Asynchronous Output Enable Input:
Low — enables output buffers (DQx pins).
High — DQx pins are high impedance.
Clock: This signal registers the address, data in, and all control signals
except G, LBO, and ZZ.
Linear Burst Order Input: This pin must remain in steady state (this
signal not registered or latched). It must be tied high or low.
Low — linear burst counter.
High — interleaved burst counter.
Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
Synchronous Address Inputs: These pins must be wired to the two
LSBs of the address bus for proper burst operation. These inputs are
registered and must meet setup and hold times.
Synchronous Byte Write Inputs: “x” refers to the byte being written
(byte a, b, c, d). SGW overrides SBx.
Synchronous Chip Enable: Active low to enable chip.
Negated high — blocks ADSP or deselects chip when ADSC is
asserted.
Synchronous Chip Enable: Active high for depth expansion.
Synchronous Chip Enable: Active low for depth expansion.
Synchronous Global Write: This signal writes all bytes regardless of the
status of the SBx and SW signals. If only byte write signals SBx are
being used, tie this pin high.
Synchronous Write: This signal writes only those bytes that have been
selected using the byte write SBx pins. If only byte write signals SBx
are being used, tie this pin low.
Sleep Mode: This active high asynchronous signal places the RAM into
the lowest power mode. The ZZ pin disables the RAMs internal clock
when placed in this mode. When ZZ is negated, the RAM remains in
low power mode until it is commanded to READ or WRITE. Data
integrity is maintained upon returning to normal operation.
NOTE: An internal pull–down is included for compatibility with SRAM
devices that do not support sleep mode. A 100% pin compatibility can
be achieved if ZZ is left open or pulled low.
Core Power Supply.
I/O Power Supply.
Ground.
No Connection: There is no connection to the chip.
89
31
K
LBO
Input
Input
32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50,
81, 82, 99, 100
36, 37
SA
SA1, SA0
Input
Input
93, 94, 95, 96
(a) (b) (c) (d)
98
SBx
SE1
Input
Input
97
92
88
SE2
SE3
SGW
Input
Input
Input
87
SW
Input
64
ZZ
Input
15, 41, 65, 91
4, 11, 20, 27, 54, 61, 70, 77
5, 10, 17, 21, 26, 40, 55, 60, 67, 71,
76, 90
14, 16, 38, 39, 42, 43, 66
VDD
VDDQ
VSS
NC
Supply
Supply
Supply
—
MCM63P737K•MCM63P819K
4
For More Information On This Product,
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MOTOROLA FAST SRAM
Freescale Semiconductor, Inc.
MCM63P737K PBGA PIN DESCRIPTIONS
Pin Locations
4B
Symbol
ADSC
Type
Input
Description
Synchronous Address Status Controller: Active low, interrupts any
ongoing burst and latches a new external address. Used to initiate a
READ, WRITE, or chip deselect.
Synchronous Address Status Processor: Active low, interrupts any
ongoing burst and latches a new external address. Used to initiate a
new READ, WRITE, or chip deselect (exception — chip deselect does
not occur when ADSP is asserted and SE1 is high).
Synchronous Address Advance: Increments address count in
accordance with counter type selected (linear/interleaved).
Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b, c, d).
4A
ADSP
Input
4G
(a) 6K, 7K, 6L, 7L, 6M, 6N, 7N, 6P, 7P
(b) 6D, 7D, 6E, 7E, 6F, 6G, 7G, 6H, 7H
(c) 1D, 2D, 1E, 2E, 2F, 1G, 2G, 1H, 2H
(d) 1K, 2K, 1L, 2L, 2M, 1N, 2N, 1P, 2P
4F
ADV
DQx
Input
I/O
G
Input
Freescale Semiconductor, Inc...
Asynchronous Output Enable Input:
Low — enables output buffers (DQx pins).
High — DQx pins are high impedance.
Clock: This signal registers the address, data in, and all control signals
except G, LBO, and ZZ.
Linear Burst Order Input: This pin must remain in steady state (this
signal not registered or latched). It must be tied high or low.
Low — linear burst counter.
High — interleaved burst counter.
Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
Synchronous Address Inputs: These pins must be wired to the two
LSBs of the address bus for proper burst operation. These inputs are
registered and must meet setup and hold times.
Synchronous Byte Write Inputs: “x” refers to the byte being written
(byte a, b, c, d). SGW overrides SBx.
Synchronous Chip Enable: Active low to enable chip.
Negated high — blocks ADSP or deselects chip when ADSC is
asserted.
Synchronous Chip Enable: Active high for depth expansion.
Synchronous Chip Enable: Active low for depth expansion.
Synchronous Global Write: This signal writes all bytes regardless of the
status of the SBx and SW signals. If only byte write signals SBx are
being used, tie this pin high.
Synchronous Write: This signal writes only those bytes that have been
selected using the byte write SBx pins. If only byte write signals SBx
are being used, tie this pin low.
Sleep Mode: This active high asynchronous signal places the RAM into
the lowest power mode. The ZZ pin disables the RAMs internal clock
when placed in this mode. When ZZ is negated, the RAM remains in
low power mode until it is commanded to READ or WRITE. Data
integrity is maintained upon returning to normal operation.
NOTE: An internal pull–down is included for compatibility with SRAM
devices that do not support sleep mode. A 100% pin compatibility can
be achieved if ZZ is left open or pulled low.
Core Power Supply.
I/O Power Supply.
Ground.
No Connection: There is no connection to the chip.
4K
3R
K
LBO
Input
Input
2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C, 6C,
2R, 6R, 3T, 4T, 5T
4N, 4P
SA
SA1, SA0
Input
Input
5L, 5G, 3G, 3L
(a) (b) (c) (d)
4E
SBx
SE1
Input
Input
2B
6B
4H
SE2
SE3
SGW
Input
Input
Input
4M
SW
Input
7T
ZZ
Input
4C, 2J, 4J, 6J, 4R
1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U
3D, 5D, 3E, 5E, 3F, 5F, 3H, 5H, 3K, 5K,
3M, 5M, 3N, 5N, 3P, 5P
1B, 7B, 1C, 7C, 4D, 3J, 5J, 4L, 1R, 5R,
7R, 1T, 2T, 6T, 2U, 3U, 4U, 5U, 6U
VDD
VDDQ
VSS
NC
Supply
Supply
Supply
—
MOTOROLA FAST SRAM
For More Information On This Product,
Go to: www.freescale.com
MCM63P737K•MCM63P819K
5
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