Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MCF51CN128
Rev. 4, 5/2009
MCF51CN128
MCF51CN128 ColdFire
Microcontroller
Cover: MCF51CN128
The MCF51CN128 device is a low-cost, low-power,
high-performance 32-bit ColdFire V1 microcontroller (MCU)
featuring 10/100 BASE-T/TX fast ethernet controller (FEC),
media independent interface (MII) to connect an external
physical transceiver (PHY), and multi-function external bus
interface.
MCF51CN128 also has multiple communication interfaces
for various ethernet gateway applications. MCF51CN128 is
the first ColdFire V1 device to incorporate ethernet and
external bus interface along with new features to minimize
power consumption and increase functionality in low-power
modes.
The MCF51CN128 features the following functional units:
• 32-bit ColdFire V1 Central Processing Unit (CPU)
– Up to 50.33 MHz ColdFire CPU from 3.6 V to 3.0 V, up
to 40 MHz CPU from 3.0 V to 2.1 V, and up to 20 MHz
CPU from 2.1 V to 1.8 V across temperature range of
–40 °C to 85 °C
– Provides 0.94 Dhrystone 2.1 MIPS per MHz
performance when running from internal RAM
(0.76 DMIPS/MHz from flash)
– ColdFire Instruction Set Revision C (ISA_C)
– Support for up to 45 peripheral interrupt requests and 7
software interrupts
• On-Chip Memory
– 128 KB Flash, 24 KB RAM
– Flash read/program/erase over full operating voltage
and temperature
– On-chip memory aliased to create a contiguous memory
space with off-chip memory
– Security circuitry to prevent unauthorized access to
Peripherals, RAM, and flash contents
• Ethernet
– FEC—10/100 BASE-T/TX, bus-mastering fast ethernet
controller with direct memory access (DMA); supports
half or full duplex; operation is limited to 3.0 V to 3.6 V
80 LQFP
14 mm
×
14 mm
64 LQFP
10 mm
×
10 mm
48 QFN
7 mm
×
7 mm
– MII—media independent interface to connect ethernet
controller to external PHY; includes output clock for
external PHY
• External Bus
– Mini-FlexBus—Multi-function external bus interface;
supports up to 1 MB memories, gate-array logic, simple
slave device or glueless interfaces to standard
chip-selected asynchronous memories
– Programmable options: access time per chip select, burst
and burst-inhibited transfers per chip select, transfer
direction, and address setup and hold times
• Power-Saving Modes
– Two low-power stop modes, one of which allows limited
use of some peripherals (ADC, KBI, RTC)
– Reduced-power wait mode shuts off CPU and allows
full use of all peripherals; FEC can remain active and
conduct DMA transfers to RAM and assert an interrupt
to wake up the CPU upon completion
– Low-power run and wait modes allow peripherals to run
while the voltage regulator is in standby
– Peripheral clock enable register can disable clocks to
unused modules, thereby reducing currents
– Low-power external oscillator that can be used in stop3
mode to provide accurate clock source to active
peripherals
– Low-power real-time counter for use in run, wait, and
stop modes with internal and external clock sources
– 6
μs
typical wake-up time from stop3 mode
– Pins and clocks to peripherals not available in smaller
packages are automatically disabled for reduced current
consumption; no user interaction is needed
• Clock Source Options
– Oscillator (XOSC) — Loop-control pierce oscillator;
crystal or ceramic resonator range of 31.25 kHz to
38.4 kHz or 1 MHz to 25 MHz
– Multi-Purpose Clock Generator (MCG) — Flexible
clock source module with either frequency-locked-loop
(FLL) or phase-lock loop (PLL) clock options. FLL can
be controlled by internal or external reference and
Freescale reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
© Freescale Semiconductor, Inc., 2009. All rights reserved.
•
•
•
•
includes precision trimming of internal reference, allowing 0.2% resolution and 2% deviation over temperature and
voltage. PLL derives a higher accuracy clock source derived by an external reference
System Protection
– Watchdog computer operating properly (COP) reset with option to run from dedicated 1-kHz internal clock source or bus
clock
– Low-voltage detection with reset or interrupt; selectable trip points
– Illegal opcode and illegal address detection with programmable reset or exception response
– Flash block protection
Development Support
– Single-wire background debug module (BDM) interface; supports same electrical interface used by the S08, 9S12, and
9S12x families debug modules
– 4 PC plus 2 address (optional data) breakpoint registers with programmable 1- or 2-level trigger response
– 64-entry processor status and debug data trace buffer with programmable start/stop conditions
Peripherals
– ADC—Up to 12 channel, 12-bit resolution; 2.5
μs
conversion time; automatic compare function; 1.7 mV/°C temperature
sensor; internal bandgap reference channel; operation in stop3; fully functional from 3.6 V to 1.8 V
– SCI—Three modules with optional 13-bit break
– SPI—Two interfaces with full-duplex or single-wire bi-directional; double-buffered transmit and receive; master or slave
mode; MSB-first or LSB-first shifting
– IIC—Two IICs with up to 100 kbps with maxmimum bus loading; multi-master operation; programmable slave address;
interrupt-driven byte-by-byte data transfer; supports broadcast mode and 11-bit addressing
– TPM—Two 3-channel, 16-bit resolution modules; selectable input capture, output compare, or buffered edge- or
center-aligned PWM on each channel
– RTC—8-bit modulus counter with binary- or decimal-based prescaler; external clock source for precise time base,
time-of-day, calendar- or task-scheduling functions; free-running on-chip low-power oscillator (1 kHz) for cyclic wake-up
without external components; runs in all MCU modes
– MTIM—Two 8-bit resolution modulo timers with 8-bit prescaler
Input/Output
– Up to 70 general-purpose input/output (GPIO) pins, all with pin mux controls to select alternate functions
– 16 keyboard interrupt (KBI) pins with selectable polarity
– Hysteresis and configurable pull-up device or input filtering on all input pins; configurable slew rate and drive strength on
all output pins
– 16 Rapid GPIO pins connected to the CPU’s high-speed local bus with set, clear, and toggle functionality (PTD and PTF)
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
2
Freescale Semiconductor
Table of Contents
1
2
3
MCF51CN128 Series Comparison . . . . . . . . . . . . . . . . . . . . . .4
1.1 Device Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.2 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . .12
3.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .12
3.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .13
3.5 ESD Protection and Latch-Up Immunity . . . . . . . . . . . .14
3.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .18
3.8 External Oscillator (XOSC) Characteristics . . . . . . . . .20
3.9 Multipurpose Clock Generator (MCG) Specifications . .21
3.10 Mini-FlexBus Timing Specifications . . . . . . . . . . . . . . .23
3.11 Fast Ethernet Timing Specifications . . . . . . . . . . . . . . .24
3.11.1 Receive Signal Timing Specifications . . . . . . . .24
3.11.2 Transmit Signal Timing Specifications . . . . . . . .25
3.11.3 Asynchronous Input Signal Timing Specifications25
3.11.4 MII Serial Management Timing Specifications .26
3.12 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
3.12.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . .26
3.12.2 TPM Module Timing . . . . . . . . . . . . . . . . . . . . .28
3.12.3 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3.12.4 ADC Characteristics . . . . . . . . . . . . . . . . . . . . .32
3.12.5 Flash Specifications. . . . . . . . . . . . . . . . . . . . . .35
3.13 EMC Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
3.13.1 Radiated Emissions . . . . . . . . . . . . . . . . . . . . . .36
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Mechanical Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . .36
6.1 80-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
6.2 64-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
6.3 48-pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Table 13..Receive Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 14..Transmit Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 15..MII Transmit Signal Timing . . . . . . . . . . . . . . . . . . . . . 25
Table 16..MII Serial Management Channel Signal Timing . . . . . 26
Table 17..Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 18..TPM Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 19..SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 20..12-bit ADC Operating Conditions . . . . . . . . . . . . . . . . 32
Table 21..12-bit ADC Characteristics (V
REFH
= V
DDAD
, V
REFL
=
V
SSAD
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 22..Flash Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 23..Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 24..Package Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 25..Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
List of Figures
Figure 1..MCF51CN128 Series Block Diagram . . . . . . . . . . . . . . 5
Figure 2..Pin Assignments in 80-Pin LQFP Package. . . . . . . . . . 6
Figure 3..Pin Assignments in 64-Pin LQFP Package. . . . . . . . . . 7
Figure 4..Pin Assignments in 48-Pin QFN Package. . . . . . . . . . . 8
Figure 5..Pull-up and Pull-down Typical Resistor Values . . . . . . 16
Figure 6..Typical Low-Side Driver (Sink) Characteristics — Low Drive
(PTxDSn = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 7..Typical Low-Side Driver (Sink) Characteristics — High
Drive (PTxDSn = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 8..Typical High-Side (Source) Characteristics — Low Drive
(PTxDSn = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 9..Typical High-Side (Source) Characteristics — High Drive
(PTxDSn = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10..Typical Run I
DD
for FBE and FEI, I
DD
vs. V
DD
(ADC off, All Other Modules Enabled) . . . . . . . . . . . . . 19
Figure 11..Typical Crystal or Resonator Circuit: High Range and Low
Range/High Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12..Typical Crystal or Resonator Circuit: Low Range/Low
Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 13..Mini-FlexBus Read Timing . . . . . . . . . . . . . . . . . . . . 23
Figure 14..Mini-FlexBus Write Timing . . . . . . . . . . . . . . . . . . . . 24
Figure 15..MII Receive Signal Timing Diagram . . . . . . . . . . . . . 25
Figure 16..MII Transmit Signal Timing Diagram . . . . . . . . . . . . . 25
Figure 17..MII Async Inputs Timing Diagram . . . . . . . . . . . . . . . 25
Figure 18..MII Serial Management Channel TIming Diagram . . 26
Figure 19..Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 20..IRQ/KBIPx Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 21..Timer External Clock. . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 22..Timer Input Capture Pulse . . . . . . . . . . . . . . . . . . . . 28
Figure 23..SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . 30
Figure 24..SPI Master Timing (CPHA =1) . . . . . . . . . . . . . . . . . 30
Figure 25..SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . 31
Figure 26..SPI Slave Timing (CPHA = 1) . . . . . . . . . . . . . . . . . . 31
Figure 27..ADC Input Impedance Equivalency Diagram . . . . . . 33
4
5
6
7
List of Tables
Table 1.. MCF51CN128 Series Device Comparison . . . . . . . . . . .4
Table 2.. Package Pin Assignments . . . . . . . . . . . . . . . . . . . . . . .8
Table 3.. Parameter Classifications . . . . . . . . . . . . . . . . . . . . . . .12
Table 4.. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .12
Table 5.. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .13
Table 6.. ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . .14
Table 7.. ESD and Latch-Up Protection Characteristics . . . . . . .14
Table 8.. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 9.. Supply Current Characteristics . . . . . . . . . . . . . . . . . . .18
Table 10..XOSC and ICS Specifications (Temperature Range = –40
to 85
°C
Ambient) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 11..MCG Frequency Specifications (Temperature Range = –40
to 125
°C
Ambient) . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 12..Mini-FlexBus AC Timing Specifications . . . . . . . . . . . .23
MCF51CN128 ColdFire Microcontroller Advance Information Data Sheet, Rev. 4
3
Freescale Semiconductor
MCF51CN128 Series Comparison
1
1.1
MCF51CN128 Series Comparison
Device Comparison
Table 1. MCF51CN128 Series Device Comparison
MCF51CN128
Feature
80-pin
Flash memory size (KB)
RAM size (KB)
V1 ColdFire core equiped with BDM (background debug
module) and 2X3 Crossbar switch
ADC (analog-to-digital converter) channels (12-bit)
FEC (Fast Ethernet Controller with MII Interface)
COP (computer operating properly)
IIC1 (inter-integrated circuit)
IIC2
IRQ (interrupt request input)
KBI (keyboard interrupts)
LVD (low-voltage detector)
MCG (multipurpose clock generator)
Port I/O
1
RGPIO (rapid general-purpose I/O)
RTC (real-time counter)
SCI1, SCI2 & SCI3 (serial communications interface)
SPI1 & SPI2 (serial peripheral interface)
TPM1 (Timer/PWM Module) channels
TPM2 channels
MTIM1 & MTIM2
External Timer Clocks
Mini-FlexBus
XOSC (crystal oscillator)
1
2
The following table compares the various device derivatives available within the MCF51CN128 series.
64-pin
128
24
Yes
12
Yes
Yes
Yes
Yes
Yes
48-pin
16
12
Yes
Yes
6
70
16
54
16
Yes
Yes
Yes
38
8
3
3
3
3
Yes
2
3
3
2
Yes
1
0
Yes
1
0
All GPIO are muxed with other functions
TMRCLK2 is not available on the 48 pin package, although MTIM2 can be used as an
internal timebase using on-chip clock sources.
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
4
Freescale Semiconductor
MCF51CN128 Series Comparison
1.2
Block Diagram
The following figure shows the connections between the MCF51CN128 series pins and modules.
ADC
BDM
Port D:
BKGD/MS
BKGD/MS/PTD6/RGPIO6
DBG
INTC
IIC2
Port C/G:
SDA2
SCL2
Port E:
KBI2P7
KBI2P6
KBI2P5
KBI2P4
KBI2P3
KBI2P2
KBI2P1
KBI2P0
Port G/I:
KBI1P7
KBI1P6
KBI1P5
KBI1P4
KBI1P3
KBI1P2
KBI1P1
KBI1P0
Port D:
ColdFire V1 core
Port E:
TPM1CH2
TPM1
TPM1CH1
TPM1CH0
Port B, F or H* : TPM1CLK
Port F/H:
TPM2CH2
TPM2
TPM2CH1
TPM2CH0
Port B, F or H* : TPM2CLK
RESET/PTC3
SIM
Port F:
RGPIO15
RGPIO14
RGPIO13
RGPIO12
RGPIO11
RGPIO10
RGPIO9
RGPIO8
Port C
KBI
Port B
Port A
VDDA/
VREFH
VSSA/
VREFL
VDDA
VREFH
VSSA
VREFL
Port C:
ADP3-
ADP0
Port D:
ADP8-
ADP4
Port E:
ADP11-
ADP9
Port C/G:
SDA1
IIC1
SCL1
PTA7/MII_RX_DV/MOSI2
PTA6/MII_RXD0/MISO2
PTA5/MII_RXD1/SPSCK2
PTA4/MII_RXD2/RXD3
PTA3/MII_RXD3/TXD3
PTA2/MII_MDC/SCL2
PTA1/MII_MDIO/SDA2
PTA0/PHYCLK
PTB7/MII_TXD2/TPM2CH1
PTB6/MII_TXD1/TPM2CH0
PTB5/MII_TXD0/SPSCK1
PTB4/MII_TX_EN/MISO1
PTB3/MII_TX_CLK/MOSI1
PTB2/MII_TX_ER/SS1
PTB1/MII_RX_ER/TMRCLK1
PTB0/MII_RX_CLK/SS2
PTC7/SDA2/SPSCK1/ADP8
PTC6/SCL2/MISO1/ADP9
PTC5/MOSI1/ADP10
PTC4/IRQ/SS1/ADP11
PTC2/MII_CRS/SDA1
PTC1/MII_COL/SCL1
PTC0/MII_TXD3/TPM2CH2
PTD7/RGPIO7/SPSCK2/ADP3
BKGD/MS/PTD6/RGPIO6
PTD5/RGPIO5/XTAL
PTD4/RGPIO4/EXTAL
PTD3/RGPIO3/RXD2/ADP4
PTD2/RGPIO2/TXD2/ADP5
PTD1/RGPIO1/RXD1/ADP6
PTD0/RGPIO0/TXD1/ADP7
PTE7/KBI2P7/FB_CS0/RXD3
PTE6/KBI2P6/FB_D0/TXD3
PTE5/KBI2P5/IRQ/TPM1CH2
PTE4/KBI2P4/CLKOUT/TPM1CH1
PTE3/KBI2P3/TPM1CH0
PTE2/KBI2P2/SS2/ADP0
PTE1/KBI2P1/MOSI2/ADP1
PTE0/KBI2P0/MISO2/ADP2
PTF7/RGPIO15/FB_A13/FB_AD13/TPM2CH2
PTF6/RGPIO14/FB_A14/FB_AD14/TPM2CH1
PTF5/RGPIO13/FB_D4/TPM2CH0
PTF4/RGPIO12/FB_D5/TMRCLK2
PTF3/RGPIO11/FB_A16/FB_AD16
PTF2/RGPIO10/FB_A17/FB_AD17
PTF1/RGPIO9/FB_A18/FB_AD18
PTF0/RGPIO8/FB_A19/FB_AD19
PTG7/KBI1P7/FB_D1
PTG6/KBI1P6/FB_D2
PTG5/KBI1P5/FB_D3
PTG4/KBI1P4/FB_RW
PTG3/KBI1P3/FB_A5/FB_AD5/SDA1
PTG2/KBI1P2/FB_A6/FB_AD6/SCL1
PTG1/KBI1P1/FB_A7/FB_AD7/SDA2
PTG0/KBI1P0/FB_A8/FB_AD8/SCL2
PTH7/FB_A9/FB_AD9/TPM2CH2
PTH6/FB_A10/FB_AD10/TPM2CH1
PTH5/FB_A11/FB_AD11
PTH4/FB_A12/FB_AD12
PTH3/FB_D6/TPM2CH0
PTH2/FB_D7/TMRCLK1
PTH1/FB_OE
PTH0/FB_A15/FB_AD15
PTJ5/FB_A0/FB_AD0
PTJ4/FB_A1/FB_AD1
PTJ3/FB_A2/FB_AD2
PTJ2/FB_A3/FB_AD3
PTJ1/FB_A4/FB_AD4
PTJ0/FB_ALE/FB_CS1
COP
LVD
FLASH
128 KB
MCG
XOSC
EXTAL
XTAL
Port A:
CLKOUT
Port E
Port D:
RXD1
TXD1
Port D:
RXD2
TXD2
Port E:
RXD3
TXD3
Port C:
SS1
SPSCK1
MOSI1
MISO1
Port H
Port J
Port G
Port F
RAM
24 KB
Port A:
MII_TX_CLK
MII_RX_CLK
MII_TX_EN
MII_TXD0
MII_TXD1
MII_TXD2
MII_TXD3
Port B:
MII_TX_ER
MII_RX_DV
MII_RXD0
MII_RXD1
MII_RXD2
MII_RXD3
MII_RX_ER
MII_CRS
Port C:
MII_COL
MII_MDC
MII_MDIO
RGPIO
Port D:
RGPIO7
RGPIO6
RGPIO5
RGPIO4
RGPIO3
RGPIO2
RGPIO1
RGPIO0
RTC
MTIM1
Port B, F or H* :
MTIM1CLK
Port B, F or H* :
MTIM2CLK
MTIM2
MII
Port F:
FB_D7-FB_D0
Port H:
FB_A19-FB_A16
FB_A11-FB_A8
Port G:
FB_CS1
FB_CS0
OE
Mini-FlexBus
FB_RW
FB_A5-FB_A2
Port I:
FB_A15-FB_A12
FB_A7-FB_A6
Port E:
FB_A1-FB_A0
SCI1
SCI2
SCI3
FEC
VDD1
VSS1
VDD2
VSS2
VDD3
VSS3
VDD4
VSS4
SPI1
VREG
External Interrupt
Port C:
IRQ
Port D/E:
SS2
SPI2
SPSCK2
MOSI2
MISO2
* TPMx and MTIMx external clocks each have the choice of being assigned to either TMRCLK1 or TMRCLK2.
Figure 1. MCF51CN128 Series Block Diagram
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
5
Port D
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