19-1090; Rev 2; 12/05
68HC11/Bidirectional-Compatible
µP Reset Circuit
General Description
The MAX6314 low-power CMOS microprocessor (µP)
supervisory circuit is designed to monitor power
supplies in µP and digital systems. The MAX6314’s
RESET
output is bidirectional, allowing it to be directly
connected to µPs with bidirectional reset inputs, such
as the 68HC11. It provides excellent circuit reliability
and low cost by eliminating external components and
adjustments. The MAX6314 also provides a debounced
manual reset input.
This device performs a single function: it asserts a reset
signal whenever the V
CC
supply voltage falls below a
preset threshold or whenever manual reset is asserted.
Reset remains asserted for an internally programmed
interval (reset timeout period) after V
CC
has risen above
the reset threshold or manual reset is deasserted.
The MAX6314 comes with factory-trimmed reset
threshold voltages in 100mV increments from 2.5V
to 5V. Preset timeout periods of 1ms, 20ms, 140ms,
and 1120ms (minimum) are also available. The device
comes in a SOT143 package.
For a µP supervisor with an open-drain reset pin, see
the MAX6315 data sheet.
Features
♦
Small SOT143 Package
♦
RESET
Output Simplifies Interface to
Bidirectional Reset I/Os
♦
Precision Factory-Set V
CC
Reset Thresholds:
100mV Increments from 2.5V to 5V
♦
±1.8% Reset Threshold Accuracy at T
A
= +25°C
♦
±2.5% Reset Threshold Accuracy Over Temp.
♦
Four Reset Timeout Periods Available:
1ms, 20ms, 140ms, or 1120ms (minimum)
♦
Immune to Short V
CC
Transients
♦
5µA Supply Current
♦
Pin-Compatible with MAX811
MAX6314
Ordering Information
PART
†
MAX6314US50D1-T
MAX6314US49D1-T
MAX6314US48D1-T
MAX6314US47D1-T
MAX6314US46D1-T
MAX6314US45D1-T
NOMINAL
V
TH
(V)
5.00
4.90
4.80
4.70
4.63
4.50
MIN t
RP
(ms)
1
1
1
1
1
1
TOP
MARK
††
AA_ _
AB_ _
AC_ _
AD_ _
AE_ _
AF_ _
________________________Applications
Computers
Controllers
Intelligent Instruments
Critical µP and µC Power Monitoring
Portable/Battery-Powered Equipment
†
The MAX6314 is available in a SOT143 package, -40°C to
+85°C temperature range.
††
The first two letters in the package top mark identify the part,
while the remaining two letters are the lot tracking code.
Typical Operating Circuit
V
CC
V
CC
Devices are available in both leaded and lead-free packaging.
Specify lead-free by replacing “-T” with “+T” when ordering.
Ordering Information continued at end of data sheet.
LASER-
TRIMMED
RESISTORS
V
CC
68HC11**
Pin Configuration
TOP VIEW
µP
4.7kΩ
RESET
MR
RESET
CIRCUITRY
GND
1
4
V
CC
MAX6314
RESET
RESET
MAX6314
GND
2
3
MR
SOT143
**OR OTHER
µC/µP
WITH BIDIRECTIONAL RESET I/O PIN.
*P
1
________________________________________________________________
Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
68HC11/Bidirectional-Compatible
µP Reset Circuit
MAX6314
ABSOLUTE MAXIMUM RATINGS
V
CC
........................................................................-0.3V to +6.0V
All Other Pins..............................................-0.3V to (V
CC
+ 0.3V)
Input Current (V
CC
) .............................................................20mA
Output Current (RESET)......................................................20mA
Rate of Rise (V
CC
) ...........................................................100V/µs
Continuous Power Dissipation (T
A
= +70°C)
SOT143 (derate 4mW/°C above +70°C) .......................320mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10sec) .............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
CC
= +2.5V to +5.5V, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
Operating Voltage Range
V
CC
Supply Current
Reset Threshold (Note 1)
Reset Threshold Tempco
V
CC
to Reset Delay
Reset Timeout Period
SYMBOL
V
CC
I
CC
V
TH
∆V
TH
/°C
V
CC
= falling at 1mV/µs
MAX6314US_ _D1-T
MAX6314US_ _D2-T
MAX6314US_ _D3-T
MAX6314US_ _D4-T
1
20
140
1120
0.8
2.4
0.3 x V
CC
0.7 x V
CC
1
100
500
32
V
CC
> 4.25V, I
SINK
= 3.2mA
RESET
Output Voltage
V
OL
V
CC
> 2.5V, I
SINK
= 1.2mA
V
CC
> 1.2V, I
SINK
= 0.5mA
V
CC
> 1.0V, I
SINK
= 80µA
RESET
INTERNAL PULLUP
Transition Flip-Flop Setup Time (Note 2)
Active Pullup Enable Threshold
RESET
Active Pullup Current
RESET
Pullup Resistance
RESET
Output Rise Time
(Note 3)
t
S
V
CC
= 5V
V
CC
= 5V
C
LOAD
= 120pF
C
LOAD
= 250pF
C
LOAD
= 200pF
C
LOAD
= 400pF
0.4
4.2
V
CC
= 3V
t
R
V
CC
= 5V
20
4.7
400
0.9
5.2
333
666
333
666
63
100
0.4
0.3
0.3
0.3
ns
V
mA
kΩ
V
µs
ns
ns
kΩ
V
CONDITIONS
T
A
= 0°C to +70°C
V
CC
= 5.5V, no load
V
CC
= 3.6V, no load
T
A
= +25°C
T
A
= -40°C to +85°C
MIN
1.0
5
4
V
TH
60
35
1.4
28
200
1570
TYP
MAX
5.5
12
10
V
TH
+ 1.8%
V
TH
+ 2.5%
UNITS
V
µA
V
ppm/°C
µs
2
40
280
2240
ms
V
TH
- 1.8%
V
TH
- 2.5%
t
RP
MANUAL RESET INPUT
MR
Input Threshold
MR
Minimum Input Pulse
MR
Glitch Rejection
MR
to Reset Delay
MR
Pullup Resistance
V
IL
V
IH
V
IL
V
IH
V
TH
> 4.0V
V
TH
< 4.0V
ns
V
Note 1:
The MAX6314 monitors V
CC
through an internal, factory-trimmed voltage divider that programs the nominal reset threshold.
Factory-trimmed reset thresholds are available in 100mV increments from 2.5V to 5V (see
Ordering and Marking Information).
Note 2:
This is the minimum time
RESET
must be held low by an external pull-down source to set the active pull-up flip-flop.
Note 3:
Measured from
RESET
V
OL
to (0.8 x V
CC
), R
LOAD
=
∞.
2
_______________________________________________________________________________________
68HC11/Bidirectional-Compatible
µP Reset Circuit
Detailed Description
The MAX6314 has a reset output consisting of a 4.7kΩ
pull-up resistor in parallel with a P-channel transistor
and an N-channel pull down (Figure 1), allowing this IC
to directly interface with microprocessors (µPs) that
have bidirectional reset pins (see the
Reset Output
section).
scratch. If, on the other hand,
RESET
is high after the
two E-clock cycle delay, the processor knows that it
caused the reset itself and can jump to a different vec-
tor and use stored state information to determine what
caused the reset.
The problem occurs with faster µPs; two E-clock cycles
is only 500ns at 4MHz. When there are several devices
on the reset line, the input capacitance and stray
capacitance can prevent
RESET
from reaching the
logic-high state (0.8 x V
CC
) in the allowed time if only a
passive pullup resistor is used. In this case, all resets
will be interpreted as external. The µP is guaranteed to
sink only 1.6mA, so the rise time cannot be much
reduced by decreasing the recommended 4.7kΩ
pullup resistance.
The MAX6314 solves this problem by including a pullup
transistor in parallel with the recommended 4.7kΩ resis-
tor (Figure 1). The pullup resistor holds the output high
until
RESET
is forced low by the µP reset I/O, or by the
MAX6314 itself. Once
RESET
goes below 0.5V, a com-
parator sets the transition edge flip-flop, indicating that
the next transition for
RESET
will be low to high. As
soon as
RESET
is released, the 4.7kΩ resistor pulls
RESET
up toward V
CC
. When
RESET
rises above 0.5V,
the active p-channel pullup turns on for the 2µs
duration of the one-shot. The parallel combination of the
4.7kΩ pullup and the p-channel transistor on-
resistance quickly charges stray capacitance on the
reset line, allowing
RESET
to transition low to high with-
in the required two E-clock period, even with several
devices on the reset line (Figure 2). Once the one-shot
times out, the p-channel transistor turns off. This
process occurs regardless of whether the reset was
caused by V
CC
dipping below the reset threshold,
MR
being asserted, or the µP or other device asserting
RESET.
Because the MAX6314 includes the standard
4.7kΩ pullup resistor, no external pullup resistor is
required. To minimize current consumption, the internal
pullup resistor is disconnected whenever the MAX6314
asserts
RESET.
MAX6314
Reset Output
A µP’s reset input starts the µP in a known state. The
MAX6314 asserts reset to prevent code-execution
errors during power-up, power-down, or brownout
conditions.
RESET
is guaranteed to be a logic low for
V
CC
> 1V (see the
Electrical Characteristics
table).
Once V
CC
exceeds the reset threshold, the internal
timer keeps reset asserted for the reset timeout period
(t
RP
); after this interval
RESET
goes high. If a brownout
condition occurs (monitored voltage dips below its pro-
grammed reset threshold),
RESET
goes low. Any time
V
CC
dips below the reset threshold, the internal timer
resets to zero and
RESET
goes low. The internal timer
starts when V
CC
returns above the reset threshold, and
RESET
remains low for the reset timeout period.
The MAX6314’s
RESET
output is designed to interface
with µPs that have bidirectional reset pins, such as the
Motorola 68HC11. Like an open-drain output, the
MAX6314 allows the µP or other devices to pull
RESET
low and assert a reset condition. However, unlike a
standard open-drain output, it includes the commonly
specified 4.7kΩ pullup resistor with a P-channel active
pullup in parallel.
This configuration allows the MAX6314 to solve a prob-
lem associated with µPs that have bidirectional reset
pins in systems where several devices connect to
RESET.
These µPs can often determine if a reset was
asserted by an external device (i.e., the supervisor IC)
or by the µP itself (due to a watchdog fault, clock error,
or other source), and then jump to a vector appropriate
for the source of the reset. However, if the µP does
assert reset, it does not retain the information, but must
determine the cause after the reset has occurred.
The following procedure describes how this is done
with the Motorola 68HC11. In all cases of reset, the µP
pulls
RESET
low for about four E-clock cycles. It then
releases
RESET,
waits for two E-clock cycles, then
checks
RESET’s
state. If
RESET
is still low, the µP con-
cludes that the source of the reset was external and,
when
RESET
eventually reaches the high state, jumps
to the normal reset vector. In this case, stored state
information is erased and processing begins from
Manual Reset Input
Many µP-based products require manual reset capabil-
ity, allowing the operator, a test technician, or external
logic circuitry to initiate a reset. A logic low on
MR
asserts reset. Reset remains asserted while
MR
is low,
and for the reset active timeout period after
MR
returns
high. To minimize current consumption, the internal
4.7kΩ pullup resistor on
RESET
is disconnected
whenever
RESET
is asserted.
_______________________________________________________________________________________
5
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