Make sure the next
Card you purchase
has...
TM
SD-14590/91/92
SYNCHRO-TO-DIGITAL CONVERTERS
FEATURES
•
Replacement for NATEL’s 1024 and
1026, and DDC’s HSDC-8915 Series
•
Quality Velocity Output
•
Accuracy to ±1.3 Arc Minutes
•
Standard 36-pin DDIP
•
Synchro or Resolver Input
•
Synthesized Reference Eliminates
180° Lock-Up
DESCRIPTION
The SD-14590/91/92 series are high reliability synchro- or resolver-
to-digital converters with 14-bit-only, 16-bit-only, or 14- or 16-bit pro-
grammable resolution. In addition, the SD-14591 and SD-14592 are
pin-for-pin replacements for the Natel 1024 and 1026, respectively,
and many legacy products.
User-programmable resolution has been designed into the SD-14590
to increase the capabilities of modern motion control systems. The
precise positioning attained at 16 bits of resolution and fast tracking
of a 14-bit device are now available from one 36-pin double DIP
hybrid. Velocity output (VEL) from the SD-14590/91/92 is a V-based
voltage of 0 to ±3.5 VDC with a linearity to 2.0%. Output voltage is
positive for an increasing angle. The digital angle output from the SD-
14590/91/92 is a natural binary code, parallel positive logic and is
TTL/CMOS compatible. Synchronization to a computer is accom-
plished via a converter busy (CB) and an inhibit (INH) input.
APPLICATIONS
Because of its high reliability, accuracy, small size, and low power
consumption, the SD-14590/91/92 is ideal for the most stringent and
severe industrial and military ground or avionics applications. All mod-
els are available with MIL-PRF-38534 processing as a standard
option. Designed with three-state output, the SD-14590/91/92 is
especially well-suited for use with computer based systems. Among
the many possible applications are radar and navigation systems, fire
control systems, flight instrumentation, and flight trainers or simula-
tors.
FOR MORE INFORMATION CONTACT:
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
Technical Support:
1-800-DDC-5757 ext. 7382
©
1996, 1999 Data Device Corporation
Data Device Corporation
www.ddc-web.com
2
SD-14590/91/92
D-02/02-250
SOLID STATE SYNCHRO INPUT OPTION
SOLID STATE RESOLVER INPUT OPTION
DIRECT INPUT OPTION
SIN
θ
COS
θ
VOLTAGE
FOLLOWER
BUFFER
SIN
θ
COS
θ
INTERNAL
DC
REFERENCE
BIT
RL
GND
+15 V
S1
S2
S3
ELECTRONIC
SCOTT T
SIN
θ
COS
θ
S1
S2
S3
S4
RESOLVER
CONDITIONER
SIN
θ
COS
θ
INPUT OPTIONS
V
REF IN
RH
REFERENCE
CONDITIONER
R
SYNTHESIZED
REF
BIT DETECT
UNITY
GAIN
BUFFER
e
UNITY
GAIN
BUFFER
VEL
SIN
θ
INPUT OPTION
COS
θ
HIGH ACCURACY
CONTROL
TRANSFORMER
GAIN
e
SIN
(θ-φ)
DEMOD
D
ERROR
PROCESSOR
VEL
T
VCO
U
E
1 LSB ANTIJITTER FEEDBACK
16 BIT CT
TRANSPARENT
LATCH
U
50 ns DELAY
T
INH
EDGE
T
TRIGGERED
LATCH
A
RESOLUTION CONTROL (14590 ONLY)
0.4-1 µs
CB
+5 V
DIGITAL
ANGLE
φ
16 BIT U-D
COUNTER
Q
INHIBIT
TRANSPARENT
LATCH
POWER
SUPPLY
CONDITIONER
INH
3 STATE
TTL BUFFER
16 BIT OUTPUT
TRANSPARENT
LATCH
3 STATE
TTL BUFFER
+10 V
INTERNAL DC
REF V (+5 V)
+15V
EM
BITS 1-8
BITS 9-14/16
EL
FIGURE 1. SD-14590/91/92 BLOCK DIAGRAM
TABLE 1. SD-14590/91/92 SPECIFICATIONS
These specifications apply over the rated power supply, temperature,
and reference frequency ranges; 10% signal amplitude variation and
10% harmonic distortion.
PARAMETER
RESOLUTION (NOTE 1)
ACCURACY (NOTE 2)
REPEATABILITY
DIFFERENTIAL LINEARITY
REFERENCE INPUT
CHARACTERISTICS
Carrier Frequency Ranges
Nominal 400 Hz Units
Nominal 60 Hz Units
Voltage Range
Input Impedance
Single Ended
Differential
Common Mode Range
SIGNAL INPUT
CHARACTERISTICS
(voltage options and minimum
input impedance balanced)
Synchro
• Zin line-to-line
• Zin each line-to-ground
Resolver
• Zin single ended
• Zin differential
• Zin each line-to-ground
Common-mode Range
Direct (1 V
L-L)
Input Signal Type
UNIT
Bits
Minutes
LSB
LSB
VALUE
14, 16, 14/16
4, 2, or 1 +1 LSB
1 max
1 max in the 16th bit
TABLE 1. SD-14590/91/92 SPECIFICATIONS (CONT.)
These specifications apply over the rated power supply, temperature,
and reference frequency ranges; 10% signal amplitude variation and
10% harmonic distortion.
PARAMETER
Output Parallel Data
UNIT
bits
VALUE
14 or 16 parallel lines; natural
binary angle, positive logic
0.4 to 2 µs positive pulse;
leading edge initiates counter
update.
Logic 1 for fault.
50 pF plus rated logic drive.
Logic 0; 1 TTL load,
1.6 mA at 0.4 Vmax
Logic 1; 10 TTL loads
0.4 mA at 2.8 Vmin
High Z; 10 µA//5 pF max
Logic 0; 100 mV max
driving CMOS
Logic 1; +5 V supply minus
100 mV min driving CMOS
See Tables 3 and 4
mV rms 3.125 16 bit mode
6.130 14 bit mode
1/3 Vs ±10%
kOhm
3 min
See TABLE 3
Converter Busy (CB)
Hz
Hz
Vrms
Ohm
Ohm
V
360 - 1000
47 - 1000
4 - 130
250k min
500k min
210 peak max
500 transient peak
BIT
Drive Capability
ANALOG OUTPUTS
Velocity (VEL)
V
Ohm
Ohm
V
Ohm
Ohm
Ohm
V
11.8 V
L-L
17.5k
11.5k
11.8 V
L-L
23k
46k
23k
25 max
90 V
L-L
130k
85k
26 V
L-L
50k
100k
50k
60 max
AC error (e)
Bias Voltage (V)
Load
DYNAMIC
CHARACTERISTICS
POWER SUPPLY
CHARACTERISTICS
Nominal Voltage
Voltage Range
Max Voltage w/o Damage
Current
TEMPERATURE RANGES
Operating
-30X
-20X
-10X
Storage
PHYSICAL
CHARACTERISTICS
Size
Sin and Cos resolver sig-
nals referenced to converter
internal DC reference V.
Vrms
1 V nominal, 1.15 V max
15 V continuous
100 V Peak Transient
Zin > 20M//10 pF
voltage follower
45 typ, 60 max
TTL/CMOS compatible
Logic 0 = 0.8 V max
Logic 1 = 2.0 V min
Loading = 30 µA max P.U.
current source
to +5 V//5pF max
CMOS transient protected
Logic 0 inhibits
Data stable after 0.5µs
Logic 0 enables
Logic 1 High Z
30µA
Logic 0 enables
Logic 1 High Z
30µA
1
0
14 bits
16 bits
Sin/Cos Voltage Range
Max Voltage w/o Damage
Input Impedance
REFERENCE SYNTHESIZER
±Sig/Ref Phase Shift
DIGITAL INPUT/OUTPUT
Logic Type
Inputs
±%
V
mA max
+15V
5
+18
25
+5V
10
+8
10
Ohm
Deg
°C
°C
°C
°C
0 to +70
-40 to +85
-55 to +125
-65 to +150
in.
(mm.)
oz
(g)
Weight
TRANSFORMER
CHARACTERISTICS
(See ordering information for
list of Transformers.
Reference Transformers are
Optional for Both Solid-State
and Voltage Follower Input
Options.)
400 Hz TRANSFORMERS
Reference Transformer
Carrier Frequency Range
Voltage Range
Input Impedance
Breakdown Voltage to GND
1.9 x 0.78 x 0.21
(48.3 x 19.8 x 5.3)
36 Pin Double Dip
0.7 max
(20)
Inhibit (INH)
Enable MSB’s (EM) (Note 3)
Pull down
Enable LSB’s (EL) (Note 3)
Pull down
Resolution Control (A)
(SD-14590 only)
(Unused Output Data Bits
Are Set to 0)
360 - 1000 Hz
18 - 130 V
40 kΩ min
1200 V peak
Data Device Corporation
www.ddc-web.com
3
SD-14590/91/92
D-02/02-250
TABLE 1. SD-14590/91/92 SPECIFICATIONS (CONT.)
These specifications apply over the rated power supply, temperature,
and reference frequency ranges; 10% signal amplitude variation and
10% harmonic distortion.
PARAMETER
VALUE
+V
S1-S3 = V
MAX
MAX
SINθ
In Phase with
RL-RH of Converter
and R2-R1 of CX.
0
360
30
90
150
210
270
330
θ
CCW
(DEGREES)
TRANSFORMER
CHARACTERISTICS (CONT’D)
Signal Transformer
360 - 1000 Hz
Carrier Frequency Range
700 V peak
Breakdown Voltage to GND
Synchro Z
IN
(Z
SO
) Resolver Z
IN
Minimum Input Impedances
(Balanced)
180
Ω
100k
Ω
90V
L-L
—
30k
Ω
26V
L-L
20k
Ω
30k
Ω
11.8V
L-L
60 Hz TRANSFORMERS
Reference Transformer
Carrier Frequency Range
Input Voltage Range
Input Impedance
Input Common Mode Voltage
Output Description
-V
MAX
S3-S2 = V
S2-S1 = V
MAX
SIN(θ
+ 120°)
MAX
SIN(θ
+ 240°)
Standard Synchro Control Transmitter (CX) Outputs as a Function of CCW
Rotation From Electrical Zero (EZ).
+V
S2-S4 = V
MAX
MAX
COS
θ
In Phase with
RH-RL of Converter
and R2-R4 of RX.
0
360
30
90
150
210
270
330
θ
CCW
(DEGREES)
47 - 440 Hz
80 - 138 V rms; 115 V rms
nominal resistive
600 KΩ min resistive
500 V rms transformer isolated
+R (in phase with RH-RL) and -R (in
phase with RL-RH) derived from op-
amps. Short-Circuit proof.
3.0 V nominal riding on ground refer-
ence V. Output Voltage level tracks
input level.
4 mA typ, 7 mA max from +15 V
supply.
47 - 440 Hz
10 - 100 V rms
L-L
; 90 V rms
L-L
nominal
148 kΩ min
L-L
balanced resistive
±500 V rms transformer isolated
Resolver Output:
- sine (-S) + cosine (+C) derived
from op-amps.
Short-circuit proof.
1.0 V rms nominal riding on ground
reference V. Output Voltage level
tracks input level.
4 mA typ, 7 mA max from +15 V
supply.
-V
MAX
S1-S3 = V
MAX
SIN(θ)
Standard Resolver Control Transmitter (RX) Outputs as a Function of CCW
Rotation From Electrical Zero (EZ) With R2-R4 Excited.
Output Voltage
FIGURE 2. SYNCHRO AND RESOLVER SIGNALS
SIGNAL INPUTS
The SD-14590/91/92 series offer three input options: synchro,
resolver, and direct. In a synchro or resolver mode, shaft angle
data is transmitted as the ratio of carrier amplitudes across the
input terminals. Synchro signals, which are of the form sinθ
cosωt, sin(θ + 120°)cosωt, and sin(θ + 240°)cosωt are internally
converted to resolver format; sinθcosωt and cosθcosωt. Direct
inputs accept 1 Vrms inputs in resolver form, (sinθcosωt and
cosθcosωt) and are buffered prior to conversion. FIGURE 2 illus-
trates synchro and resolver signals as a function of the angle
θ.
The solid-state signal and reference inputs are true differential
inputs with high AC and DC common mode rejection. Input
impedance is maintained with power off.
Power Required
Signal Transformer
Carrier Frequency Range
Input Voltage Range
Input Impedance
Input Common Mode Voltage
Output Description
Output Voltage
Power Required
NOTES:
1. Pin programmable for SD-14590 only; SD-14591 is 14 bits and
SD-14592 is 16 bits
2. See TABLE 6.
3. See Logic Input/Output section.
SOLID-STATE BUFFER INPUT PROTECTION:
TRANSIENT VOLTAGE SUPPRESSION
The solid-state signal and reference inputs are true differential
inputs with high AC and DC common rejection so most applica-
tions will not require units with isolation transformers. Input
impedance is maintained with power off. The current AC peak
+DC common mode voltage should not exceed the values in
TABLE 1.
90 V line-to-line systems may have voltage transients which
exceed the 500 V specification. These transients can destroy the
thin-film input resistor network in the hybrid. Therefore, 90 V
L-L
solid-state input modules may be protected by installing voltage
suppressors as shown. Voltage transients are likely to occur
whenever synchro or resolver inputs are switched on and off. For
SD-14590/91/92
D-02/02-250
INTRODUCTION
The circuit shown in FIGURE 1, the SD-14590/91/92 block dia-
gram, consists of three main parts: the signal input; a feedback
loop whose elements are the control transformer, demodulator,
error processor, VCO and up-down counter; and digital interface
circuitry including various latches and buffers.
Data Device Corporation
www.ddc-web.com
4
FOR 90 V SYNCHRO INPUTS
CR1
S1
CR2
S3
S3
RH
CR3
S2
RL
S1
HYBRID
1N6071A
SYNTHESIZED REFERENCE
The synthesized reference section of the SD-14590 eliminates
errors caused by quadrature voltage. Due to the inductive nature
of synchros and resolvers, their signals lead the reference signal
(RH and RL) by about 6°. When an uncompensated reference
signal is used to demodulate the control transformer’s output,
quadrature voltages are not completely eliminated. In a 14-bit
converter it is not necessary to compensate for the reference sig-
nal’s phase shift. A 6° phase shift will, however, cause problems
for the one minute accuracy converters. As shown in FIGURE 1,
the converter synthesizes its own cos(ωt +
α)
reference signal
from the sinθcos(ωt +
α),
cosθcos(ωt +
α)
signal inputs and from
the cosωt reference input. The phase angle of the synthesized
reference is determined by the signal input. The reference input
is used to choose between the +180° and -180° phases. The
synthesized reference will always be exactly in phase with the
signal input, and quadrature errors will therefore be eliminated.
The synthesized reference circuit also eliminates the 180° false
error null hangup.
Quadrature voltages in a resolver or synchro are by definition the
resulting 90° fundamental signal in the nulled out error voltage
(e) in the converter. A digital position error will result due to the
interaction of this quadrature voltage and a reference phase shift
between the converter signal and reference inputs. The magni-
tude of this error is given by the following formula:
Error = Quad/Full Scale (FS) signal * tan(α)
Where: Error is in radians
Quad/FS signal is per unit quadrature input level.
α
= signal to reference phase shift in degrees.
A typical example of the magnitude of this source of error is as
follows:
Quad/FS signal = .001
α
=6
Error = 0.35 min
≈1
LSB in the 16th bit.
Note:
Quad/FS is composed of static quadrature which is specified by the
resolver or synchro supplier plus the speed voltage which is given by:
S2
CR1, CR2, and CR3 are 1N6068A, bipolar transient voltage suppressors or
equivalent.
FOR 90 V RESOLVER INPUTS
S1
S2
90 V L-L
RESOLVER
INPUT
S3
S4
CR4
CR5
S3
S4
S1
S2
HYBRID
1N6071A
CR4 and CR5 are 1N6068A, bipolar transient voltage suppressors or equivalent.
FIGURE 3. CONNECTIONS FOR VOLTAGE
TRANSIENT SUPPRESSORS
instance, a 1000 V transient can be generated when the primary
of a CX or TX driving a synchro or resolver input is opened. See
FIGURE 3.
FEEDBACK LOOP
The feedback loop produces a digital angle
φ
which tracks the
analog input angle
θ
to within the specified accuracy of the con-
verter. The control transformer performs the following trigono-
metric computation:
sin(θ -
φ)
= sinθ cosφ - cosθ sinφ
where
θ
is the angle representing the resolver shaft position, and
φ
is the digital angle contained in the up/down counter. The track-
ing process consists of continually adjusting
φ
to make (θ -
φ)
=
0, so that
φ
will represent the shaft position
θ.
The output of the
demodulator is an analog DC level proportional to sin(θ -
φ).
The
error processor receives its input from the demodulator and inte-
grates this sin(θ -
φ)
error signal which then drives a Voltage
Controlled Oscillator (VCO). The VCO’s clock pulses are accu-
mulated by the up/down counter. The velocity voltage accuracy,
linearity and offset are determined by the quality of the VCO.
Functionally, the up/down counter is an incremental integrator.
Therefore, there are two stages of integration which make the
converter a Type II tracking servo. In a Type II servo, the VCO
always settles to a counting rate which makes dφ/dt equal to
dθ/dt without a lag. The output data will always be fresh and
available as long as the maximum tracking rate of the converter
is not exceeded.
Speed Voltage = rotational speed/carrier frequency
Where: Speed Voltage is the per unit ratio of electrical
rotational speed in RPS divided by carrier frequency in Hz.
This error is totally negligible for 14-bit converters. For 16-bit con-
verters where the highest accuracy possible is needed and
where the quadrature and phase shift specifications can be high-
er, this source of error could be significant. The reference syn-
thesizer circuit in the converter which derives the reference from
the input signal essentially sets
α
to zero resulting in complete
rejection of the quadrature.
Data Device Corporation
www.ddc-web.com
5
SD-14590/91/92
D-02/02-250
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
