MC9S08QD4 Series Features
8-Bit HCS08 Central Processor Unit (CPU)
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Flash block protect
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16 MHz HCS08 CPU (central processor
unit)
HC08 instruction set with added BGND
instruction
Background debugging system
Breakpoint capability to allow single
breakpoint setting during in-circuit
debugging (plus two more breakpoints in
on-chip debug module)
Support for up to 32 interrupt/reset sources
Peripherals
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Memory
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Flash read/program/erase over full
operating voltage and temperature
Flash size:
— MC9S08QD4/S9S08QD4: 4096 bytes
— MC9S08QD2/S9S08QD2: 2048 bytes
RAM size
— MC9S08QD4/S9S08QD4: 256 bytes
— MC9S08QD2/S9S08QD2: 128 bytes
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ADC
— 4-channel, 10-bit analog-to-digital
converter with automatic compare
function, asynchronous clock source,
temperature sensor and internal bandgap
reference channel. ADC is hardware
triggerable using the RTI counter.
TIM1
— 2-channel timer/pulse-width
modulator; each channel can be used for
input capture, output compare, buffered
edge-aligned PWM, or buffered
center-aligned PWM
TIM2
— 1-channel timer/pulse-width
modulator; each channel can be used for
input capture, output compare, buffered
edge-aligned PWM, or buffered
center-aligned PWM
KBI
— 4-pin keyboard interrupt module
with software selectable polarity on edge or
edge/level modes
Input/Output
Power-Saving Modes
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Wait plus three stops
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Clock Source Options
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ICS
— Internal clock source module (ICS)
containing a frequency-locked-loop (FLL)
controlled by internal. Precision trimming
of internal reference allows 0.2% resolution
and 2% deviation over temperature and
voltage.
Four General-purpose input/output (I/O)
pins, one input-only pin and one
output-only pin. Outputs 10 mA each, 60
mA maximum for package.
Software selectable pullups on ports when
used as input
Software selectable slew rate control and
drive strength on ports when used as output
Internal pullup on RESET and IRQ pin to
reduce customer system cost
System Protection
Development Support
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Watchdog computer operating properly
(COP) reset with option to run from
dedicated 32 kHz internal clock source or
bus clock
Low-voltage detection with reset or
interrupt
Illegal opcode detection with reset
Illegal address detection with reset
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Single-wire background debug interface
Package Options
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8-pin SOIC package
8-pin PDIP (Only for MC9S08QD4 and
MC9S08QD2)
All package options are RoHS compliant
FPGA/CPLD
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