RDC-19220/2S
Make sure the next
Card you purchase
has...
®
16-BIT MONOLITHIC TRACKING
RESOLVER-TO-DIGITAL (R/D) CONVERTER
FEATURES
•
Accuracy up to 1.3 Arc Minutes
•
Internal Synthesized Reference
•
+5 Volt Only Option
•
Programmable:
- Resolution: 10-, 12-, 14-, or 16-Bit
- Bandwidth
- Tracking Rate
•
Differential Resolver Input Mode
•
Velocity Output Eliminates
Tachometer
•
Built-In-Test (BIT) Output,
No 180° Hangup
DESCRIPTION
The RDC-19220/2S is a low-cost, versatile, state-of-the-art 16-bit
monolithic Resolver-to-Digital (R/D) Converter. This single chip con-
verter offers programmable features such as resolution, bandwidth
and velocity output scaling.
Resolution programming allows selection of 10, 12, 14, or 16 bits,
with accuracies to 1.3 minutes. This feature combines the high track-
ing rate of a 10-bit converter with the precision and low-speed veloc-
ity resolution of a 16-bit converter in one package.
The internal Synthesized Reference section eliminates errors due to
quadrature voltage. Previously, a 6 degree phase shift caused prob-
lems for a 16-bit converter. The synthesized reference capability
ensures operation with a phase shift up to 45 degrees. The velocity
output (VEL) from the RDC-19220/2S, which can be used to replace
a tachometer, is a 4 V signal referenced to ground. The full-scale
value of VEL is set by the user with a single resistor.
The RDC-19220/2S converter is available with operating temperature
ranges of 0° to +70°C, -40° to +85°C, and -55° to +125°C.
•
-55° to +125°C Operating
Temperature
•
Class K and MIL-PRF-38534 Options
APPLICATIONS
The low cost, small size, high accuracy, and versatile performance of
the RDC-19220/2S converter makes it ideal for use in modern high
performance industrial control systems. Typical applications include
motor control, radar antenna positioning, machine tool control, robot-
ics, and process control. Class K and MIL-PRF-38534 processing is
available for space and military applications.
FOR MORE INFORMATION CONTACT:
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
Technical Support:
1-800-DDC-5757 ext. 7382
©
1999, 2000 Data Device Corporation
Data Device Corporation
www.ddc-web.com
RDC-19220
SERIES
SYNTHESIZED
REFERENCE
(RDC1922XS ONLY)
SIGNAL
INPUTS
SIN
-S
+S
COS
-C
+C
+5C
+CAP
-CAP
-5C
A GND
+5 V
GND
-5 V
-
+
A B
-
+
CONTROL
TRANSFORMER
GAIN
REFERENCE
INPUT
+REF -REF
BIT
EXTERNAL
COMPONENTS
(RC MAY BE LEFT
UNCONNECTED)
VSUM
C
BW
R
1
DEMODULATOR
C
BW
10
R
B
VEL
2
RDC-19220/2S
F-05/03-0
HYSTERESIS
16-BIT
UP/DOWN
COUNTER
E
DATA
LATCH
VCO
&
TIMING
INTEGRATOR
R
V
-5 V
INVERTER
(RDC-19222
ONLY)
VCO
R
S
R
C
POWER SUPPLY
INPUTS/GROUND
INH
EM BIT 1 EL
THRU
BIT 16
A B
RESOLUTION
CONTROL
CB
DIGITAL
OUTPUT
FIGURE 1. RDC-19220/2S BLOCK DIAGRAM
TABLE 1. RDC-19220/2S SPECIFICATIONS
These specifications apply over the rated power supply, temperature,
and reference frequency ranges; 10% signal amplitude variation & 10% harmonic distortion.
PARAMETER
RESOLUTION
FREQUENCY RANGE
ACCURACY -XX2
-XX3
(NOTE 3)
Repeatability
Differential Linearity
FREQUENCY RANGE
ACCURACY -XX5
(NOTE 3)
Repeatability
Differential Linearity
REFERENCE
Type
Voltage: differential
single ended
overload
Frequency
Input Impedance
±Sig/Ref Phase Shift
SIGNAL INPUT
Type
Voltage: operating
overload
Input Impedance
DIGITAL INPUT/OUTPUT
Logic Type
Inputs
UNIT
Bits
Hz
Min
Min
LSB
LSB
Hz
Min
LSB
LSB
VALUE
10, 12, 14, or 16 (notes 1 & 2)
1k - 4k
4 +1 LSB
2 +1 LSB
±1
±1
1k - 5k (note 8)
1 +1 LSB
±1
±1
47-1k (note 4)
4 +1 LSB
2 +1 LSB
±1
±1
47-1k (note 4)
1 +1 LSB
±1
±1
4k - 10k
5 +1 LSB
3 +1 LSB
±2
±2
V
V
V
Hz
Ohm
deg
(+REF, -REF)
Differential
±10 max (note 9)
±5 max (note 9)
±25 continuous 100 transient
DC to 10,000 (note 8)
10M min //20 pf
45 max from 400 Hz to 10 kHz (note 5)
(+S, -S, SIN, +C, -C, COS)
Resolver, differential, groundbased
2 ±15%
±25 continuous
10M min //10 pf.
TTL/CMOS compatible
Logic 0 = 0.8 V max. / Logic 1 = 2.0 V min.
Loading=10 µA max P.U. current source to +5 V //5 pF max., CMOS transient protected
Logic 0 inhibits; Data stable within 0.1 µS
Logic 0 enables; Data stable within 150 nS
Logic 1 = High Impedance, Data High Z within 100 nS
Mode
Resolver
“
“
“
LVDT
“
“
“
B
0
0
1
1
-5 V
0
1
-5 V
A
0
1
0
1
0
-5 V
-5 V
-5 V
Resolution
10 bits
12 bits
14 bits
16 bits
8 bits
10 bits
12 bits
14 bits
Vrms
V
Ohm
Inhibit (INH)
Enable Bits 1 to 8 (EM)
Enable Bits 9 to 16 (EL)
Resolution and Mode Control (A & B)
(see notes 1 and 2)
Outputs
Parallel Data (1-16)
Converter Busy (CB)
Built-in-Test (BIT)
10, 12, 14 or 16 parallel lines; natural binary angle positive logic (see note 2)
0.25 to 0.75 µs positive pulse leading edge initiates counter update.
Logic 0 for BIT condition.
±100 LSBs of error with a filter of 500 µS total, Loss-of-Signal (LOS) less than 500 mV, or
Loss-of-Reference (LOR) less than 500 mV.
50 pF+
Logic 0; 1 TTL load, 1.6 mA at 0.4 V max.
Logic 1; 10 TTL loads, -0.4 mA at 2.8 V min
Logic 0; 100 mV max driving CMOS
Logic 1; +5 V supply minus 100 mV min driving CMOS High Z; 10 uA //5 pF max
Drive Capability
Notes: 1. Unused data bits are set to logic “0.”
2. In LVDT mode, bit 16 is LSB for 14-bit resolution or bit 12 is LSB for 10-bit resolution
3. Accuracy in LVDT mode is 0.15% + 1 LSB of full scale.
4. If the frequency is between 47Hz and 1kHz, then there may be 1 LSB of jitter at quadrant boundaries.
5. The maximum phase shift tolerance will degrade linearly from 45 degrees at 400 Hz to 30 degrees at 60 Hz.
6. See text, General Setup Considerations.
7. When using internally generated -5V the internal -5V charge pump when measured at the converter pin, may be as low as -20% (or -4V).
8.-XX5 accuracy is 1minute + 1 LSB up to 5 kHz max.
9. A signal less than 500 mV will assert BIT.
Data Device Corporation
www.ddc-web.com
3
RDC-19220/2S
F-05/03-0
TABLE 1. RDC-19220/2S SPECIFICATIONS (CONT.)
PARAMETER
DYNAMIC
CHARACTERISTICS
Resolution
Tracking Rate-min (note 6)
Bandwidth(Closed Loop) Max
Ka
A1
A2
A
B
Acceleration (1 LSB lag)
Settling Time(179° step)
UNIT
VALUE
(at maximum bandwidth)
bits
rps
Hz
1/sec
2
1/sec
1/sec
1/sec
1/sec
deg/s
2
msec
10
1152
1200
5.7M
19.5
295k
2400
1200
2M
2
12
288
1200
5.7M
19.5
295k
2400
1200
500k
8
14
72
600
1.4M
4.9
295k
1200
600
30k
20
16
18
300
360k
1.2
295k
600
300
2k
50
THEORY OF OPERATION
The RDC-19220/2S series of converter is a single CMOS custom
monolithic chip. It is implemented using mixed signal CMOS
technology which merges precision analog circuitry with digital
logic to form a complete high-performance tracking resolver-to-
digital converter. For user flexibility and convenience, the con-
verter bandwidth, dynamics, and velocity scaling are externally
set with passive components.
FIGURE 1 is the RDC-19220/2S Functional Block Diagram. The
converter operates with ±5 V DC power supplies. Analog signals
are referenced to analog ground, which is at ground potential.
The converter is made up of two main sections; a converter and
a digital interface. The converter front-end consists of sine and
cosine differential input amplifiers. These inputs are protected to
±25 V with 2 kΩ resistors and diode clamps to the ±5 V DC sup-
plies. These amplifiers feed the high accuracy Control
Transformer (CT). Its other input is the 16-bit digital angle
φ.
Its
output is an analog error angle, or difference angle, between the
two inputs. The CT performs the ratiometric trigonometric com-
putation of SINθCOSφ - COSθSINφ = SIN(θ-φ) using amplifiers,
switches, logic and capacitors in precision ratios.
Note:
The transfer function of the CT is normally trigonometric, but in LVDT mode
the transfer function is triangular (linear) and could thereby convert any lin-
ear transducer output.
VELOCITY
CHARACTERISTICS
Positive for increasing angle
Polarity
V
±4 (at nominal ps)
Voltage Range(Full Scale)
%
10 typ
20 max
Scale Factor Error
PPM/C 100 typ
200 max
Scale Factor TC
%
0.75 typ 1.3 max
Reversal Error
%
0.25 typ 0.50 max
Linearity
mV 5 typ
10 max
Zero Offset
µV/C 15 typ
30 max
Zero Offset TC
kΩ
8 max
Load
0.125 min, 2 max
Noise
Vp/V 1 typ
POWER SUPPLIES
Nominal Voltage
Voltage Range
Max Volt. w/o Damage
Current
TEMPERATURE RANGE
Operating
-30X
-20X
-10X
Storage
THERMAL RESISTANCE
Junction to Case,
θjc
40-Pin DDIP (Ceramic)
44-Pin J-Lead (Plastic)
44-Pin J-Lead (Ceramic)
PHYSICAL
CHARACTERISTICS
Size: 40-pin DDIP
44-pin J-lead
Weight:
40-pin DDIP
44-pin J-lead
(notes 6 and 7)
+5
-5
±5
±5
+7
-7
14 typ, 22 max (each)
V
%
V
mA
°C
°C
°C
°C
0 to +70
-40 to +85
-55 to +125
-65 to +150
The converter accuracy is limited by the precision of the com-
puting elements in the CT. For enhanced accuracy, the CT in
these converters use capacitors in precision ratios, instead of the
more conventional precision resistor ratios. Capacitors used as
computing elements with op-amps need to be sampled to elimi-
nate voltage drifting. Therefore, the circuits are sampled at a high
rate (70 kHz) to eliminate this drifting and at the same time to
cancel out the op-amp offsets.
The error processing is performed using the industry standard
technique for type II tracking R/D converters. The DC error is
integrated yielding a velocity voltage which in turn drives a volt-
age-controlled oscillator (VCO). This VCO is an incremental inte-
grator (constant voltage input to position rate output) which,
together with the velocity integrator, forms a type II servo feed-
back loop. A lead in the frequency response is introduced to sta-
bilize the loop and a lag at higher frequency is introduced to
reduce the gain and ripple at the carrier frequency and above.
The settings of the various error processor gains and break fre-
quencies are done with external resistors and capacitors so that
the converter loop dynamics can be easily controlled by the user.
°C/W 4.6
°C/W 72.6
°C/W 2.4
in(mm) 2.0 x 0.6 x 0.2 (50.8 x 15.24 x 5.08)
in(mm) 0.690 square (17.526)
Plastic
N/A
0.08 (2.27)
Ceramic
0.24 (6.80)
0.064 (1.84)
oz (g)
oz (g)
Data Device Corporation
www.ddc-web.com
4
RDC-19220/2S
F-05/03-0
TRANSFER FUNCTION AND BODE PLOT
The dynamic performance of the converter can be determined
from its Transfer Function Block Diagrams and its Bode Plots
(open and closed loop). These are shown in FIGURES 2, 3, and 4.
The open loop transfer function is as follows:
GENERAL SETUP CONDITIONS
DDC has external component selection software which consid-
ers all the criteria below and, in a simple fashion, asks the key
parameters (carrier frequency, resolution, bandwidth, and track-
ing rate) to derive the external component values.
The following recommendations should be considered when
installing the RDC-19220/2S Resolver-to-Digital (R/D) converter:
1) When setting the bandwidth (BW) and Tracking Rate (TR)
(selecting five external components), the system require-
ments need to be considered. For the greatest noise immuni-
ty, select the minimum BW and TR the system will allow.
2) Power supplies are ±5V DC. For lowest noise performance it
is recommended that a 0.1µF or larger cap be connected from
each supply to ground near the converter package.
3) Resolver inputs and velocity output are referenced to AGND.
This pin should be connected to GND near the converter
package. Digital currents flowing through ground will not dis-
turb the analog signals.
4) The BIT output, which is active low, is activated by an error of
approximately 100 LSBs. During normal operation, for step
inputs or on power up, a large error can exist.
Open Loop Transfer Function =
(
S + 1
)
B
S
S
(
10B + 1
)
A
2
2
where:
A is the gain coefficient
A
2
= A
1
A
2
B is the frequency of lead compensation
The components of gain coefficient are error gradient, integrator
gain, and VCO gain. These can be broken down as follows:
- Error Gradient = 0.011 volts per LSB (CT+Error
Amp+Demod with 2 Vrms input)
- Integrator gain =
- VCO Gain =
C
S
F
S
1.1C
BW
volts per second per volt
1
LSBs per second per volt
1.25 R
v
C
vco
C
s
= 10 pF
F
s
= 70 kHz when Rs = 30 kΩ
F
s
= 100 kHz when Rs = 20 kΩ
F
s
= 125 kHz when Rs = 15 kΩ
C
vco
= 50 pF
where:
ERROR PROCESSOR
RESOLVER
INPUT
(θ)
+
-
CT
e
A1 S + 1
B
S S +1
10B
VELOCITY
OUT
VCO
A
2
S
DIGITAL
POSITION
OUT (φ)
R
V
, R
B
, and C
BW
are selected by the user to set velocity scaling
and bandwidth.
H=1
FIGURE 3. TRANSFER FUNCTION BLOCK DIAGRAM #2
-1
2d
RB C
BW
VEL
C
BW
/10
RS
-VSUM
VEL
-VCO
50 pf
C
VCO
CT
RESOLVER
INPUT
(θ)
+
GAIN
DEMOD
1
C
S
F
S
11 mV/LSB
±1.25 V
THRESHOLD
R
V
GAIN = 4
2A
OPEN LOOP
B
A
-6
db
b/o
(CRITICALLY DAMPED)
(B = A/2)
ct
ω
(rad/sec)
10B
/oc
t
GAIN = 0.4
R1
VCO
-
16 BIT
UP/DOWN
COUNTER
f
BW
= BW (Hz) =
H=1
DIGITAL
OUTPUT
(φ)
2A
π
CLOSED LOOP
2A
2 2A
ω
(rad/sec)
FIGURE 2. TRANSFER FUNCTION BLOCK DIAGRAM #1
FIGURE 4. BODE PLOTS
Data Device Corporation
www.ddc-web.com
5
RDC-19220/2S
F-05/03-0
微控制器 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
