Preliminary
GS8182R08/18/36BD-333/300/250/200/167
165-Bump BGA
Commercial Temp
Industrial Temp
Features
• Simultaneous Read and Write SigmaCIO™ Interface
• Common I/O bus
• JEDEC-standard pinout and package
• Double Data Rate interface
• Byte Write (x36 and x18) and Nybble Write (x8) function
• Burst of 4 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation with self-timed Late Write
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• Pin-compatible with present 9Mb, 36Mb, and 72Mb and
future 144Mb devices
• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
18Mb SigmaCIO DDR-II
Burst of 4 SRAM
333 MHz–167 MHz
1.8 V V
DD
1.8 V and 1.5 V I/O
Bottom View
165-Bump, 13 mm x 15 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
clock inputs, not differential inputs. If the C clocks are tied
high, the K clocks are routed internally to fire the output
registers instead.
Common I/O x36 and x18 SigmaCIO DDR-II B4 RAMs
always transfer data in four packets. When a new address is
loaded, A0 and A1 preset an internal 2 bit linear address
counter. The counter increments by 1 for each beat of a burst of
four data transfer. The counter always wraps to 00 after
reaching 11, no matter where it starts.
Common I/O x8 SigmaCIO DDR-II B4 RAMs always transfer
data in four packets. When a new address is loaded, the LSBs
are internally set to 0 for the first read or write transfer, and
incremented by 1 for the next 3 transfers. Because the LSBs
are tied off internally, the address field of a x8 SigmaCIO
DDR-II B4 RAM is always two address pins less than the
advertised index depth (e.g., the 2M x 8 has a 512K
addressable index).
SigmaCIO™ Family Overview
The GS8182R08/18/36BD are built in compliance with the
SigmaCIO DDR-II SRAM pinout standard for Common I/O
synchronous SRAMs. They are 16,777,216-bit (18Mb)
SRAMs. The GS8182R08/18/36BD SigmaCIO SRAMs are
just one element in a family of low power, low voltage HSTL
I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS8182R08/18/36BD SigmaCIO DDR-II SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer. The device also allows the user to manipulate the
output register clock inputs quasi independently with the C and
C clock inputs. C and C are also independent single-ended
Parameter Synopsis
-333
tKHKH
tKHQV
3.0 ns
0.45 ns
-300
3.3 ns
0.45 ns
-250
4.0 ns
0.45 ns
-200
5.0 ns
0.45 ns
-167
6.0 ns
0.5 ns
Rev: 1.00a 6/2007
1/35
© 2007, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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