Advance v0.4
ProASIC 3 nano Flash FPGAs
Features and Benefits
Wide Range of Features
• 10 k to 250 k System Gates
• Up to 36 kbits of True Dual-Port SRAM
• Up to 71 User I/Os
®
®
Advanced I/Os
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—up to 4 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V
• Wide Range Power Supply Voltage Support per JESD8-B,
Allowing I/Os to Operate from 2.7 V to 3.6 V
• I/O Registers on Input, Output, and Enable Paths
• Selectable Schmitt Trigger Inputs
• Hot-Swappable and Cold-Sparing I/Os
• Programmable Output Slew Rate
†
and Drive Strength
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the ProASIC3 Family
†
• Up to Six CCC Blocks, One with an Integrated PLL
• Configurable Phase Shift, Multiply/Divide, Delay
Capabilities and External Feedback
• Wide Input Frequency Range (1.5 MHz to 350 MHz)
Reprogrammable Flash Technology
•
•
•
•
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
Live at Power-Up (LAPU) Level 0 Support
Single-Chip Solution
Retains Programmed Design when Powered Off
High Performance
• 350 MHz System Performance
In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption via JTAG (IEEE 1532–compliant)
†
• FlashLock
®
to Secure FPGA Contents
Clock Conditioning Circuit (CCC) and PLL
Low Power
•
•
•
•
Low-Power ProASIC3 nano Products
1.5 V Core Voltage for Low Power
Support for 1.5 V-Only Systems
Low-Impedance Flash Switches
Embedded Memory
• 1 kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
†
• True Dual-Port SRAM (except ×18 organization)
†
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
Enhanced Commercial Temperature Range
• –20°C to +70°C
Table 1 •
ProASIC3 nano Devices
ProASIC3 nano Devices
System Gates
Typical Equivalent Macrocells
VersaTiles (D-flip-flops)
RAM kbits (1,024 bits)
4,608-Bit
Blocks
2
2
2
A3PN010
10 k
86
260
–
–
1k
–
–
4
2
34
34
QN48
A3PN015
15 k
128
384
–
–
1k
–
–
4
3
49
–
QN68
A3PN020
20 k
172
520
–
–
1k
–
–
4
3
49
52
QN68
A3PN030
1
30 k
256
768
–
–
1k
–
–
6
2
77
83
QN48, QN68
VQ100
A3PN060
60 k
512
1,536
18
4
1k
Yes
1
18
2
71
71
A3PN125
125 k
1,024
3,072
36
8
1k
Yes
1
18
2
71
71
A3PN250
250 k
2,048
6,144
36
8
1k
Yes
1
18
4
68
68
FlashROM Bits
Secure (AES) ISP
Integrated PLL in CCCs
2
VersaNet Globals
I/O Banks
Maximum User I/Os (packaged device)
Maximum User I/Os (Known Good Die)
Package Pins
QFN
VQFP
VQ100
VQ100
VQ100
Notes:
1. A3PN030 is available in the Z feature grade only and offers package compatibility with the lower density nano devices. Refer to
"ProASIC3 nano Ordering Information" on page III.
2. A3PN030 and smaller devices do not support this feature.
3. For higher densities and support of additional features, refer to the
ProASIC3
and
ProASIC3E
handbooks.
† A3PN030 and smaller devices do not support this feature.
January 2009
© 2009 Actel Corporation
I
ProASIC3 nano Flash FPGAs
I/Os Per Package
ProASIC3 nano Devices
Known Good Die
QN48
QN68
VQ100
Notes:
1. A3PN030 is available in the Z feature grade only and offers package compatibility with the lower density nano devices.
Refer to
"ProASIC3 nano Ordering Information" on page III
.
2. When considering migrating your design to a lower- or higher-density device, refer to the
ProASIC3 Handbook
to ensure
compliance with design and board migration requirements.
3. "G" indicates RoHS-compliant packages. Refer to
"ProASIC3 nano Ordering Information" on page III
for the location of
the "G" in the part number. For nano devices, the VQ100 package is offered in both leaded and RoHS-compliant
versions. All other packages are RoHS-compliant only.
Table 2 •
ProASIC3 nano FPGAs Package Sizes Dimensions
Packages
Length × Width (mm\mm)
Nominal Area (mm
2
)
Pitch (mm)
Height (mm)
QN48
6x6
36
0.4
0.90
QN68
8x8
64
0.4
0.90
VQ100
14 x 14
196
0.5
1.20
A3PN010
34
34
49
49
A3PN015
–
A3PN020
52
A3PN030
1
83
34
49
77
71
71
68
A3PN060
71
A3PN125
71
A3PN250
68
II
A d v a n c e v 0 .4
ProASIC3 nano Flash FPGAs
ProASIC3 nano Ordering Information
A3PN250
_
Z
1
VQ
G
100
I
Application (Temperature Range)
Blank =
Commercial
(
–
20°C to +70°C Ambient Temperature)
I = Industrial (
–
40°C to +85°C Ambient Temperature)
PP = Pre-Production
ES = Engineering
Sample
(Room Temperature Only)
Package Lead
Count
Lead-Free Packaging
Blank =
Standard
Packaging
G=
RoHS-Compliant Packaging
Package Type
QN = Quad Flat Pack No Leads (0.4 mm and 0.5 mm pitches)
VQ = Very Thin Quad Flat Pack (0.5 mm pitch)
DIELOT = Known
Good
Die
Speed Grade
1
F = 20%
Slower
than
Standard
Blank =
Standard
1 = 15% Faster than
Standard
2 = 25% Faster than
Standard
Feature
Grade
Z = nano
devices
without enhanced features
2
Blank =
Standard
Part Number
ProASIC3 nano Devices
A3PN010 = 10,000
System Gates
A3PN015 = 15,000
System Gates
A3PN020 = 20,000
System Gates
A3PN030 = 30,000
System Gates
A3PN060 =
60,000 System Gates
A3PN125 = 125,000
System Gates
A3PN250 = 250,000
System Gates
Notes:
1. The DC and switching characteristics for the –F speed grade targets are based only on simulation. The characteristics
provided for the –F speed grade are subject to change after establishing FPGA specifications. Some restrictions might be
added and will be reflected in future revisions of this document. The –F speed grade is supported only in the commercial
temperature range.
2. For the A3PN060, A3PN125, and A3PN250, the Z feature grade does not support the enhanced nano features of Schmitt
trigger input, cold-sparing, and hot-swap I/O capability. The A3PN030 Z feature grade does not support Schmitt trigger
input. For the VQ100, CS81, UC81, QN68, and QN48 packages, the Z feature grade and the N part number are not marked
on the device.
Device Marking
Actel normally topside marks the full ordering part number on each device. There are some exceptions to this, such as some
of the Z feature grade nano devices, the V2 designator for IGLOO devices, and packages where space is physically limited.
Packages that have limited characters available are UC36, UC81, CS81, QN48, QN68, and QFN132. On these specific packages,
a subset of the device marking will be used that includes the required legal information and as much of the part number as
allowed by character limitation of the device. In this case, devices will have a truncated device marking and may exclude the
applications markings, such as the I designator for Industrial Devices or the ES designator for Engineering Samples.
Advance v0.4
III
ProASIC3 nano Flash FPGAs
Figure 1
shows an example of device marking based on the AGL030V5-UCG81. The actual mark will vary by the
device/package combination ordered.
Device Name
(six
characters)
Package
Wafer Lot #
ACTELXXX
AGL030YWW
UCG81XXXX
XXXXXXXX
Country
of Origin
Date
Code
Customer
Mark
(if applicable)
Figure 1 •
Example of Device Marking for Small Form Factor Packages
ProASIC3 nano Product Available in the Z Feature Grade
Devices
Packages
A3PN030
QN48
QN68
VQ100
A3PN060
–
–
VQ100
A3PN125
–
–
VQ100
A3PN250
–
–
VQ100
Temperature Grade Offerings
ProASIC3 nano Devices
QN48
QN68
VQ100
Notes:
1. C = Commercial temperature range: –20°C to 70°C ambient temperature
2. I = Industrial temperature range: –40°C to 85°C ambient temperature
A3PN010
C, I
–
–
A3PN015
–
C, I
–
A3PN020
–
C, I
–
A3PN030
C, I
C, I
C, I
A3PN060
–
–
C, I
A3PN125
–
–
C, I
A3PN250
–
–
C, I
Speed Grade and Temperature Grade Matrix
Temperature Grade
C
2
I
3
Notes:
1. The characteristics provided for the –F speed grade are subject to change after establishing FPGA specifications. Some
restrictions might be added and will be reflected in future revisions of this document. The –F speed grade is supported
only in the commercial temperature range.
2. C = Commercial temperature range: –20°C to 70°C ambient temperature.
3. I = Industrial temperature range: –40°C to 85°C ambient temperature.
Contact your local Actel representative for device availability:
http://www.actel.com/contact/default.aspx.
–F
1
Std.
✓
–
✓
✓
IV
A d v a n c e v 0 .4
1 – ProASIC3 nano Device Overview
General Description
ProASIC3, the third-generation family of Actel flash FPGAs, offers performance, density, and
features beyond those of the ProASIC
PLUS®
family. Nonvolatile flash technology gives ProASIC3
nano devices the advantage of being a secure, low-power, single-chip solution that is live at power-
up (LAPU). ProASIC3 nano devices are reprogrammable and offer time-to-market benefits at an
ASIC-level unit cost. These features enable designers to create high-density systems using existing
ASIC or FPGA design flows and tools.
ProASIC3 nano devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as
well as clock conditioning circuitry based on an integrated phase-locked loop (PLL). A3PN030 and
smaller devices do not have PLL or RAM support. ProASIC3 nano devices have up to 250,000 system
gates, supported with up to 36 kbits of true dual-port SRAM and up to 71 user I/Os.
ProASIC3 nano devices increase the breadth of the ProASIC3 product line by adding new features
and packages for greater customer value in high volume consumer, portable, and battery-backed
markets. Added features include smaller footprint packages designed with two-layer PCBs in mind,
low power, hot-swap capability, and Schmitt trigger for greater flexibility in low-cost and power-
sensitive applications.
Flash Advantages
Reduced Cost of Ownership
Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike
SRAM-based FPGAs, flash-based ProASIC3 nano devices allow all functionality to be live at power-
up; no external boot PROM is required. On-board security mechanisms prevent access to all the
programming information and enable secure remote updates of the FPGA logic. Designers can
perform secure remote in-system reprogramming to support future design iterations and field
upgrades with confidence that valuable intellectual property (IP) cannot be compromised or
copied. Secure ISP can be performed using the industry-standard AES algorithm. The ProASIC3
nano device architecture mitigates the need for ASIC migration at higher user volumes. This makes
the ProASIC3 nano device a cost-effective ASIC replacement solution, especially for applications in
the consumer, networking/communications, computing, and avionics markets.
With a variety of devices under $1, Actel ProASIC3 nano FPGAs enable cost-effective
implementation of programmable logic and quick time to market.
Security
Nonvolatile, flash-based ProASIC3 nano devices do not require a boot PROM, so there is no
vulnerable external bitstream that can be easily copied. ProASIC3 nano devices incorporate
FlashLock, which provides a unique combination of reprogrammability and design security without
external overhead, advantages that only an FPGA with nonvolatile flash programming can offer.
ProASIC3 nano devices utilize a 128-bit flash-based lock and a separate AES key to secure
programmed intellectual property and configuration data. In addition, all FlashROM data in
ProASIC3 nano devices can be encrypted prior to loading, using the industry-leading AES-128
(FIPS192) bit block cipher encryption standard. The AES standard was adopted by the National
Institute of Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard. ProASIC3
nano devices have a built-in AES decryption engine and a flash-based AES key that make them the
most comprehensive programmable logic device security solution available today. ProASIC3 nano
devices with AES-based security allow for secure, remote field updates over public networks such as
the Internet, and ensure that valuable IP remains out of the hands of system overbuilders, system
cloners, and IP thieves. The contents of a programmed ProASIC3 nano device cannot be read back,
although secure design verification is possible.
A dv a n c e v 0. 4
1-1
FPGA/CPLD
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