Data Sheet No.PD94717 revF
IR3623MPbF
HIGH FREQUENCY 2-PHASE, SINGLE OR DUAL OUTPUT SYNCHRONOUS STEP
DOWN CONTROLLER WITH OUTPUT TRACKING AND SEQUENCING
Description
Features
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Dual Synchronous Controller with 180
o
Out of Phase
Operation
Configurable to 2-Independent Outputs or Current
Share Single Output
Output Voltage Tracking
Power up /down Sequencing
Current Sharing Using Inductor’s DCR
+/-1% Accurate Reference Voltage
Programmable Switching Frequency up 1200kHz
Programmable Over Current Protection
Hiccup Current Limit Using MOSFET R
DS(on)
sensing
Latched Overvoltage Protection
Dual Programmable Soft-Starts
Enable
Pre-Bias Start-up
Dual Power Good Outputs
On Board Regulator
External Frequency Synchronization
Thermal Protection
32-Lead MLPQ Package
Embedded Telecom Systems
Distributed Point of Load Power Architectures
Computing Peripheral Voltage Regulator
Graphics Card
General DC/DC Converters
The IR3623 IC is a high performance
Synchronous Buck PWM Controller that can be
configured for two independent outputs or as a
current sharing single output. Since the IC does
not contain integrated MOSFET drivers it is ideal
for controlling iPOWIR
TM
integrated power stage
modules such as the iP2005 series of products.
IR3623 enables output tracking and sequencing
of multiple rails in either ratiometric or
simultaneous fashion. The IR3623 features 180
o
out of phase operation which reduces the
required input/output capacitance. The switching
frequency is programmable from 200kHz to
1200kHz per phase by use of an external resistor
or the switching frequency can be synchronized
to an external clock signal. Other key features
offered by the IR3623 include; two independent
programmable soft starts, two independent power
good outputs, precision enable input and under
voltage lockout. The current limit is provided by
sensing the low side MOSFET's on-resistance for
optimum cost and performance. The output
voltages are monitored through dedicated pins to
protect against open circuit and to improve
response time to an overvoltage event.
Applications
Vo1
Vo2
Vo1
Vo2
Ratiometric Powerup
Ratiometric Powerdown
Vo1
Vo2
Vo1
Vo2
Simultaneous Powerup
Simultaneous Powerdown
Fig. 1: Power Up /Down Sequencing
ORDERING INFORMATION
PKG
DESIG
M
M
PACKAGE
DESCRIPTION
IR3623MPbF
IR3623MTRPbF
PIN
COUNT
32
32
PARTS
PARTS
PER TUBE PER REEL
73
-------
--------
3000
T&R
ORIANTAION
Fig A
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IR3623MPbF
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to GND)
•Vcc
Supply Voltage ...............................................… -0.5V to 16V
•PWM1,
PWM2 …………………….………….……….. -0.5V to 16V
•PGood
………. ……………………………………….. -0.5V to 16V
•Gnd
to SGnd ………………………………………… +/- 0.3V
•Storage
Temperature Range .................................... -65°C To 150°C
•Operating
Junction Temperature Range .................. -40°C To 125°C
•ESD
Classification …………………………………… JEDEC, JESD22-A114
Caution:
Stresses above those listed in “Absolute Maximum Rating” may cause permanent damage to the
device. These are stress ratings only and function of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications is not implied. Exposure to “Absolute Maximum Rating”
conditions for extended periods may affect device reliability.
Package Information
5V
_sn
s
En
ab
le
Rt
Gn
d
SG
nd
V
R
EF
2
32
PGood1 1
PGood2 2
Track2 3
V
SEN2
4
OVP_Output
5
31
30
29
28 27
V
P
26
25
24 Seq
23 Sync
22 Track1
V
P
1
Pad
21 V
SEN1
20
19
OCGnd
Fb1
Fb2 6
Comp2 7
SS2/SD2/Mode 8
9
10
11
12
C
18 Comp1
17 SS1/SD1
13
UT
3
14
15
16
OC
Se
t2
Ph
_E
n2
PW
M2
V
C
Θ
JA
= 36
o
C/W
Θ
JC
= 1
o
C/W
*Exposed pad on underside is connected to a copper
pad through vias for 4-layer PCB board design
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PW
M1
Ph
_E
n1
OC
Se
t1
V
O
2
IR3623MPbF
Recommended Operating Conditions
Symbol
Vcc
Fs
Tj
Definition
Supply Voltage
Operating frequency
Junction temperature
Min
8.5
200
-40
Max
14.5
1200
125
Units
V
kHz
o
C
Electrical Specifications
Unless otherwise specified, these specification apply over Vcc=12V, 0
o
C<Tj<105
o
C
Parameter
Output Voltage Accuracy
FB1, FB2 Voltage
Accuracy
-40 C<Tj< 125 C,
Note2
o
o
SYM
Test Condition
Min
TYP
MAX
Units
V
FB
-1
-2.5
0.8
+1
+1.35
V
%
%
Supply Current
V
CC
Supply Current
(Static)
I
CC
(Static)
SS=0V, No Switching
-
10
17
mA
Under Voltage Lockout
V
CC
-Threshold
V
CC
-Hysteresis
Enable-Threshold
Enable-Hysteresis
5V_sns-Threshold
5V_sns_Hysteresis
V
CC
_UVLO(R)
V
CC
_UVLO(F)
Vcc-Hyst
En_UVLO(R)
En_UVLO(F)
En_Hyst
5V_sns_UVLO(R)
5V_sns_UVLO(F)
5V_sns_Hyst
I
(drive)
Supply ramping up
Supply ramping down
Supply ramping up / down
Supply ramping up
Supply ramping down
Supply ramping up / down
Supply ramping up
Supply ramping down
Supply ramping up / down
7.6
6.9
400
1.2
1.0
4.55
4.3
8.00
7.4
600
1.2
100
4.6
100
10
V
out3
-1
0.8
8.4
7.9
800
1.4
1.35
4.85
4.8
V
V
mV
V
V
mV
V
V
mV
mA
V
V
Ph_En, PWM 1,2
Drive Current
Input Voltage High
Input Voltage Low
Internal Regulator
Output Accuracy
Output Curret
V
out3
Io
F
S
Fs(range)
Vramp
Dmin
Dmin(ctrl)
Dmax
Rt=51K
See Figure 16
Note1
Fb=1V
F
S
=300kHz,
Note1
F
S
=300kHz, Fb=0.6V
20% above free running Freq
200
Note1
Note1
2
0.8
300
85
2400
7.6V<Vcc<14.5V
Isource=0 to 200mA
4.9
200
510
200
1.25
0
150
600
690
1200
5.15
5.4
V
mA
kHz
kHz
V
%
ns
%
kHz
ns
V
V
Oscillator
Frequency
Frequency Range
Ramp Amplitude
Min Duty Cycle
Min Pulse Width
Max duty Cycle
Sync Frequency Range
Sync Pulse Duration
Sync High Level
Threshold
Sync Low Level
Threshold
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3
IR3623MPbF
Electrical Specifications
Parameter
Error Amplifier
Fb Voltage Input
Bias Current
E/A Source/Sink
Current
Transconductance
Input offset Voltage
VP Voltage Range
Track Voltage
Range
IFB
I
(source/Sink)
gm1,2
Voffset
VP
Track
Fb to Vref
Note1
Note1
SS=3V
120
2800
-3
0
0
-0.1
200
-0.5
280
4400
+3
V
CC
-2
V
CC
-2
μA
μA
μmho
mV
V
V
SYM
Test Condition
Min
TYP
MAX
Units
Soft Start/SD
Soft Start Current
Shutdown Output
Threshold
OCSET Current
Hiccup Current
Hiccup Duty Cycle
ISS
SD
Source / Sink
17
22
27
0.25
μA
V
Over Current Protection
I
OCSET
I
Hiccup
Hiccup(duty)
17
Note1
I
Hiccup
/I
OCSET
,
Note1
22
3
15
27
μA
uA
%
Over Voltage Protection
OVP Trip Threshold
OVP Fault Prop
Delay
OVP_Output Current
OVP(trip)
OVP(delay)
Output Forced to
1.125Vref
10
20
1.1Vref
1.15Vref
1.2Vref
5
V
μ
s
mA
Thermal Shutdown
Thermal shutdown
Thermal shutdown
Hysteresis
Note1
135
20
o
o
C
C
Seq Input
Seq Threshold
Seq
On
Off
Vsen Ramping Down
I
PGood
=2mA
2.0
0.3
0.8Vref
0.9Vref
0.1
0.95Vref
0.5
V
V
V
Power Good
Vsen Lower Trip
point
PGood Output Low
Voltage
Vsen(trip)
PG(voltage)
Note1: Guaranteed by design but not test in production
Note2: Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested
in production
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4
IR3623MPbF
Pin#
1
2
3
4
5
6
7
8
Pin Name
PGood1
PGood2
Track2
V
SEN2
OVP-Output
Fb2
Comp2
SS2/SD2/Mode
Description
Power Good pin out put for channel 1, open collector. This pin
needs to be externally pulled high
Power Good pin out put for channel 2, open collector. This pin
needs to be externally pulled high
Sets the type of power up / down sequencing (ratiometric or
simultaneously). If it is not used connect this pin to Vout3.
Sense pin for OVP2 and Power Good 2, Channel 2. If it is not used
connect this pin to Gnd.
OVP output, goes high when OVP condition occurs
Inverting inputs to the error amplifier2. If it is not used connect this
pin to Gnd
Compensation pin for the error amplifier2
Soft start for channel 2, can be used as SD pin. Float this pin for
current share single output application. If it is not used connect this
pin to Gnd.
Current limit set point for channel2
Phase Enable pin for channel2
PWM output for channel2
Supply Voltage for the internal blocks of the IC
Output of the internal regulator
PWM output for channel1
Phase Enable pin for channel1
Current limit set point for Channel 1
Soft start for channel 1, can be used as SD pin
Compensation pin for the error amplifier1
Inverting input to the error amplifier1
Ground connection for OCset circuit
Sense pin for OVP1 and Power Good, Channel 1
Sets the type of power up / down sequencing (ratiometric or
simultaneously). If it is not used connect this pin to Vout3.
External synchronization pin
Enable pin for tracking and sequencing
Non inverting input of error amplifier1
Non inverting input of error amplifier2. If it is not used connect this
pin to Gnd.
Reference Voltage
Signal Ground
IC’s Ground
Connecting a resistor from this pin to ground sets the Switching
frequency
Enable pin, recycling this pin will rest OV, SS and Prebias latch
Sensing either external 5V or the Vout3
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
OCSet2
Ph_En2
PWM2
Vcc
V
out3
PWM1
Ph_En1
OCSet1
SS1/SD1
Comp1
Fb1
OCGnd
V
SEN1
Track1
Sync
Seq
V
P1
V
P2
V
REF
SGnd
Gnd
Rt
Enable
5V_sns
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