IR3507Z
DATA SHEET
XPHASE3
TM
PHASE IC
DESCRIPTION
The IR3507Z Phase IC combined with an IR
XPhase3
TM
Control IC provides a full featured and flexible way to
implement power solutions for the latest high performance CPUs and ASICs. The “Control” IC provides
overall system control and interfaces with any number of “Phase” ICs which each drive and monitor a single
phase of a multiphase converter. The
XPhase3
TM
architecture results in a power supply that is smaller, less
expensive, and easier to design while providing higher efficiency than conventional approaches.
FEATURES IR3507Z PHASE IC
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Power State Indicator (PSI) interface provides the capability to maximize the efficiency at light loads.
7V/2A gate drivers (4A GATEL sink current)
Converter output voltage up to 5.1 V (Limited to VCCL-1.4V)
Loss-less inductor current sensing
Feed-forward voltage mode control
Integrated boot-strap synchronous PFET
Only four external components per phase
3 wire analog bus connects Control and Phase ICs (VID, Error Amp, IOUT)
3 wire digital bus for accurate daisy-chain phase timing control without external components
Anti-bias circuitry prevents excessive sag in output voltage during PSI de-assertion
PSI input is ignored during power up
Debugging function isolates phase IC from the converter
Self-calibration of PWM ramp, current sense amplifier, and current share amplifier
Single-wire bidirectional average current sharing
Small thermally enhanced 20L 4 X 4mm MLPQ package
RoHS compliant
APPLICATION CIRCUIT
Figure 1 Application Circuit
Page 1 of 19
IR Confidential
April 2, 2009
IR3507Z
ORDERING INFORMATION
Part Number
IR3507ZMTRPBF
* IR3507ZMPBF
* Samples only
Package
20 Lead MLPQ
(4 x 4 mm body)
20 Lead MLPQ
(4 x 4 mm body)
Order Quantity
3000 per reel
100 piece strips
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. These are stress ratings only and functional operation of the device at these or any other
conditions beyond those indicated in the operational sections of the specifications are not implied.
Operating Junction Temperature…………….. 0 to 150
o
C
Storage Temperature Range………………….-65
o
C to 150
o
C
ESD Rating………………………………………HBM Class 1C JEDEC Standard
MSL Rating………………………………………2
Reflow Temperature…………………………….260
o
C
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
PIN NAME
IOUT
PSI
DACIN
LGND
PHSIN
NC
PHSOUT
CLKIN
PGND
GATEL
NC
VCCL
BOOST
GATEH
SW
V
MAX
8V
8V
3.3V
n/a
8V
n/a
8V
8V
0.3V
8V
n/a
8V
40V
40V
34V
V
MIN
-0.3V
-0.3V
-0.3V
n/a
-0.3V
n/a
-0.3V
-0.3V
-0.3V
-0.3V DC, -5V for
100ns
n/a
-0.3V
-0.3V
-0.3V DC, -5V for
100ns
-0.3V DC, -5V for
100ns
-0.3V
-0.3V
-0.3V
-0.3V
n/a
I
SOURCE
1mA
1mA
1mA
n/a
1mA
n/a
2mA
1mA
5A for 100ns,
200mA DC
5A for 100ns,
200mA DC
n/a
n/a
1A for 100ns,
100mA DC
3A for 100ns,
100mA DC
3A for 100ns,
100mA DC
n/a
1mA
1mA
1mA
n/a
I
SINK
1mA
1mA
1mA
n/a
1mA
n/a
2mA
1mA
n/a
5A for 100ns,
200mA DC
n/a
5A for 100ns,
200mA DC
3A for 100ns,
100mA DC
3A for 100ns,
100mA DC
n/a
10mA
1mA
1mA
1mA
n/a
16
VCC
34V
17
CSIN+
8V
18
CSIN-
8V
19
EAIN
8V
20
NC
n/a
Note:
1. Maximum GATEH – SW = 8V
2. Maximum BOOST – GATEH = 8V
Page 2 of 19
IR Confidential
April 2, 2009
IR3507Z
RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN
8.0V
≤
V
CC
≤
28V, 4.75V
≤
V
CCL
≤
7.5V, 0
o
C
≤
T
J
≤
125
o
C. 0.5V
≤
V(DACIN)
≤
1.6V, 500kHz
≤
CLKIN
≤
9MHz, 250kHz
≤
PHSIN
≤1.5MHz
ELECTRICAL CHARACTERISTICS
The electrical characteristics involve the spread of values guaranteed within the recommended operating conditions.
Typical values represent the median values, which are related to 25°C.
C
GATEH
= 3.3nF, C
GATEL
= 6.8nF (unless otherwise specified).
PARAMETER
Gate Drivers
GATEH Source Resistance
GATEH Sink Resistance
GATEL Source Resistance
GATEL Sink Resistance
GATEH Source Current
GATEH Sink Current
GATEL Source Current
GATEL Sink Current
GATEH Rise Time
GATEH Fall Time
GATEL Rise Time
GATEL Fall Time
GATEL low to GATEH high
delay
GATEH low to GATEL high
delay
Disable Pull-Down
Resistance
Clock
CLKIN Threshold
CLKIN Bias Current
CLKIN Phase Delay
PHSIN Threshold
PHSOUT Propagation
Delay
PHSIN Pull-Down
Resistance
PHSOUT High Voltage
PHSOUT Low Voltage
TEST CONDITION
BOOST – SW = 7V. Note 1
BOOST – SW = 7V. Note 1
VCCL – PGND = 7V. Note 1
VCCL – PGND = 7V. Note 1
BOOST=7V, GATEH=2.5V, SW=0V.
BOOST=7V, GATEH=2.5V, SW=0V.
VCCL=7V, GATEL=2.5V, PGND=0V.
VCCL=7V, GATEL=2.5V, PGND=0V.
BOOST – SW = 7V, measure 1V to 4V
transition time
BOOST – SW = 7V, measure 4V to 1V
transition time
VCCL – PGND = 7V, Measure 1V to 4V
transition time
VCCL – PGND = 7V, Measure 4V to 1V
transition time
BOOST = VCCL = 7V, SW = PGND = 0V,
measure time from GATEL falling to 1V to
GATEH rising to 1V
BOOST = VCCL = 7V, SW = PGND = 0V,
measure time from GATEH falling to 1V to
GATEL rising to 1V
Note 1
MIN
TYP
1.0
1.0
1.0
0.4
2.0
2.0
2.0
4.0
5
5
10
5
10
20
MAX
2.5
2.5
2.5
1.0
UNIT
Ω
Ω
Ω
Ω
A
A
A
A
ns
ns
ns
ns
ns
10
10
20
10
40
10
20
40
ns
30
80
130
kΩ
Compare to V(VCCL)
CLKIN = V(VCCL)
Measure time from CLKIN<1V to GATEH>1V
Compare to V(VCCL)
Measure time from CLKIN > (VCCL * 50% )
to PHSOUT > (VCCL *50%), 10pF Load
@125
o
C
40
-0.5
40
35
4
45
0.0
75
50
15
57
0.5
125
55
35
%
µA
ns
%
ns
30
I(PHSOUT) = -10mA, measure VCCL –
PHSOUT
I(PHSOUT) = 10mA
1
100
0.6
0.4
170
kΩ
V
1
V
Page 3 of 19
IR Confidential
April 2, 2009
IR3507Z
PARAMETER
PWM Comparator
PWM Ramp Slope
Input Offset Voltage
EAIN Bias Current
Minimum Pulse Width
Minimum GATEH Turn-off
Time
Current Sense Amplifier
CSIN+/- Bias Current
CSIN+/- Bias Current
Mismatch
Input Offset Voltage
Gain
Unity Gain Bandwidth
Slew Rate
Differential Input Range
Differential Input Range
Common Mode Input Range
Rout at T
J
= 25
o
C
Rout at T
J
= 125
o
C
IOUT Source Current
IOUT Sink Current
Share Adjust Amplifier
Input Offset Voltage
Differential Input Range
Gain
Unity Gain Bandwidth
PWM Ramp Floor Voltage
Maximum PWM Ramp Floor
Voltage
Minimum PWM Ramp Floor
Voltage
PSI Comparator
Rising Threshold Voltage
Falling Threshold Voltage
Hysteresis
Resistance
Floating Voltage
TEST CONDITION
Vin=12V
Note 1
0
≤
EAIN
≤
3V
Note 1
MIN
42
-5
-5
20
TYP
52.5
0
-0.3
55
80
MAX
57
5
5
70
160
UNIT
mV/
%DC
mV
µA
ns
ns
Note 1
CSIN+ = CSIN- = DACIN. Measure
input referred offset from DACIN
0.5V
≤
V(DACIN) < 1.6V
C(IOUT)=10pF. Measure at IOUT.
Note 1
0.8V
≤
V(DACIN)
≤
1.6V, Note 1
0.5V
≤
V(DACIN) < 0.8V, Note 1
Note 1
Note 1
-200
-50
-1
30.0
4.8
0
0
0
32.5
6.8
6
200
50
1
35.0
8.8
nA
nA
mV
V/V
MHz
V/µs
mV
mV
V
kΩ
kΩ
mA
mA
mV
V
V/V
kHz
mV
mV
mV
-10
-5
0
2.3
3.6
0.5
0.5
-3
-1
4
4
-116
120
-220
3.0
4.7
1.6
1.4
0
5.0
8.5
0
180
-160
50
50
Note2
3.7
5.4
2.9
2.9
3
1
6
17
116
240
-100
Note 1
Note 1
CSIN+ = CSIN- = DACIN. Note 1
Note 1
IOUT Open, Measure relative to DACIN
IOUT = DACIN – 200mV. Measure
relative to floor voltage.
IOUT = DACIN + 200mV. Measure
relative to floor voltage.
Note 1
Note 1
Note 1
520
400
50
200
800
620
550
70
500
700
650
120
850
1150
mV
mV
mV
kΩ
mV
Page 4 of 19
IR Confidential
April 2, 2009
IR3507Z
PARAMETER
Body Brake Comparator
Threshold Voltage with EAIN
decreasing
Threshold Voltage with EAIN
increasing
Hysteresis
Propagation Delay
TEST CONDITION
Measure relative to Floor Voltage
Measure relative to Floor Voltage
MIN
-300
-200
70
40
TYP
-200
-100
105
65
MAX
-110
-10
130
90
UNIT
mV
mV
mV
ns
VCCL = 5V. Measure time from EAIN <
V(DACIN) (200mV overdrive) to GATEL
transition to < 4V.
OVP Comparator
OVP Threshold
Step V(IOUT) up until GATEL drives
high. Compare to V(VCCL)
Propagation Delay
V(VCCL)=5V, Step V(IOUT) up from
V(DACIN) to V(VCCL). Measure time to
V(GATEL)>4V.
Synchronous Rectification Disable Comparator
Threshold Voltage
The ratio of V(CSIN-) / V(DACIN), below
which V(GATEL) is always low.
Negative Current Comparator
Input Offset Voltage
Note 1
Propagation Delay Time
Apply step voltage to V(CSIN+) –
V(CSIN-). Measure time to V(GATEL)<
1V.
Bootstrap Diode
Forward Voltage
I(BOOST) = 30mA, VCCL = 6.8V
Debug Comparator
Threshold Voltage
Compare to V(VCCL)
General
VCC Supply Current
8V
≤
V
(
VCC) < 10V
VCC Supply Current
10V
≤
V
(
VCC)
≤
16V
VCCL Supply Current
BOOST Supply Current
4.75V
≤
V
(
BOOST)-V(SW )≤ 8V
DACIN Bias Current
SW Floating Voltage
-1.0
15
-0.8
40
-0.4
70
V
ns
66
75
86
%
-16
100
0
200
16
400
mV
ns
360
-250
1.1
1.1
3.1
0.5
-1.5
0.1
520
-150
4.0
2.0
8.0
1.5
-0.75
0.3
960
-50
6.1
4
12.1
3
1
0.4
mV
mV
mA
mA
mA
mA
µA
V
Note 1:
Guaranteed by design, but not tested in production
Note 2:
V
CCL
-0.5V or V
CC
– 2.5V, whichever is lower
Page 5 of 19
IR Confidential
April 2, 2009
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
