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SN75C1154
QUADRUPLE LOW-POWER DRIVERS/RECEIVERS
SLLS151C – DECEMBER 1988 – REVISED MARCH 1997
D
D
D
D
D
D
D
D
Meets or Exceeds the Requirements of
ANSI EIA/TIA-232-E and ITU
Recommendation V.28
Very Low Power Consumption
5 mW Typ
Wide Driver Supply Voltage . . .
±
4.5 V
to
±
15 V
Driver Output Slew Rate Limited to
30 V/µs Max
Receiver Input Hysteresis . . . 1000 mV Typ
Push-Pull Receiver Outputs
On-Chip Receiver 1-µs Noise Filter
Functionally interchangeable With Motorola
MC145404
DW OR N PACKAGE
(TOP VIEW)
V
DD
1RA
1DY
2RA
2DY
3RA
3DY
4RA
4DY
V
SS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
1RY
1DA
2RY
2DA
3RY
3DA
4RY
4DA
GND
description
The SN75C1154 is a low-power BiMOS device containing four independent drivers and receivers that are used
to interface data terminal equipment (DTE) with data circuit-terminating equipment (DCE). This device has been
designed to conform to ANSI EIA/TIA-232-E. The drivers and receivers of the SN75C1154 are similar to those
of the SN75C188 quadruple driver and SN75C189A quadruple receiver, respectively. The drivers have a
controlled output slew rate that is limited to a maximum of 30 V/µs and the receivers have filters that reject input
noise pulses of shorter than 1
µs.
Both these features eliminate the need for external components.
The SN75C1154 is designed using low-power techniques in a BiMOS technology. In most applications, the
receivers contained in these devices interface to single inputs of peripheral devices such as ACEs, UARTs, or
microprocessors. By using sampling, such peripheral devices are usually insensitive to the transition times of
the input signals. If this is not the case or for other uses, it is recommended that the SN75C1154 receiver outputs
be buffered by single Schmitt input gates or single gates of the HCMOS, ALS, or 74F logic families.
The SN75C1154 is characterized for operation from 0°C to 70°C.
logic symbol
†
1RA
2RA
3RA
4RA
1DY
2DY
3DY
4DY
2
4
6
8
3
5
7
9
19
17
15
13
18
16
14
12
1RY
2RY
3RY
4RY
1DA
2DA
3DA
4DA
logic diagram (positive logic)
typical of each receiver
RA
2, 4, 6, 8
19, 17, 15, 13
RY
typical of each driver
DY
3, 5, 7, 9
18, 16, 14, 12
DA
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
©
1997, Texas Instruments Incorporated
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1
SN75C1154
QUADRUPLE LOW-POWER DRIVERS/RECEIVERS
SLLS151C – DECEMBER 1988 – REVISED MARCH 1997
schematics of inputs and outputs
EQUIVALENT DRIVER INPUT
VDD
EQUIVALENT DRIVER OUTPUT
VDD
Input
DA
Internal
1.4-V Reference
VSS
GND
160
Ω
74
Ω
Output
DY
72
Ω
VSS
Input
RA
EQUIVALENT RECEIVER INPUT
3.4 kΩ
EQUIVALENT RECEIVER OUTPUT
VCC
1.5 kΩ
ESD
Protection
ESD
Protection
530
Ω
GND
Output
RY
GND
Resistor values shown are nominal.
2
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SN75C1154
QUADRUPLE LOW-POWER DRIVERS/RECEIVERS
SLLS151C – DECEMBER 1988 – REVISED MARCH 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage, V
DD
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
Supply voltage, V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 15 V
Supply voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage range, V
I
: Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
SS
to V
DD
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 30 V to 30 V
Output voltage range, V
O
: Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V
SS
– 6 V) to (V
DD
+ 6 V)
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to (V
CC
+ 0.3 V)
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, T
A
: SN75C1154 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are with respect to the network GND terminal.
DISSIPATION RATING TABLE
PACKAGE
DW
N
TA
≤
25°C
POWER RATING
1125 mW
1150 mW
DERATING FACTOR
ABOVE TA = 25°C
9.0 mW/°C
9.2 mW/°C
TA = 70°C
POWER RATING
720 mW
736 mW
recommended operating conditions
MIN
Supply voltage, VDD
Supply voltage, VSS
Supply voltage, VCC
Input voltage VI
voltage,
High-level input voltage, VIH
Low-level input voltage, VIL
High-level output current, IOH
High-level output current, IOL
Operating free-air temperature, TA
Driver
Receiver
Driver
Receiver
0
2
0.8
–1
3.2
70
4.5
– 4.5
4.5
VSS+2
NOM
12
– 12
5
MAX
15
– 15
6
VDD
±
25
UNIT
V
V
V
V
V
mA
mA
°C
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3
SN75C1154
QUADRUPLE LOW-POWER DRIVERS/RECEIVERS
SLLS151C – DECEMBER 1988 – REVISED MARCH 1997
DRIVER SECTION
electrical characteristics over operating free-air temperature range, V
DD
= 12 V, V
SS
= –12 V,
V
CC
= 5 V
±10%
(unless otherwise noted)
PARAMETER
VOH
VOL
IIH
IIL
IOS(H)
IOS(L)
IDD
ISS
High-level
High level output voltage
Low-level output voltage
g
(see Note 2)
High-level input current
Low-level input current
High-level short circuit
g
output current‡
Low-level short circuit
output current‡
Supply current from VDD
Supply current from VSS
VIL = 0.8 V,
,
See Figure 1
,
VIH = 2 V,
See Figure 1
VI = 5 V,
VI = 0,
VI = 0 8 V
0.8 V,
VI = 2 V
V,
TEST CONDITIONS
RL = 3 kΩ,
,
,
RL = 3 kΩ,
See Figure 2
See Figure 2
VO = 0 or VSS,
VO = 0 or VDD,
See Figure 1
See Figure 1
VDD = 5 V,
VDD = 12 V
VDD = 5 V,
VDD = 12 V
VSS = – 5 V
VSS = – 12 V
VSS = – 5 V
VSS = – 12 V
–7 5
7.5
7.5
75
– 12
12
115
115
– 115
– 115
VDD = 5 V,
VDD = 12 V,
VDD = 5 V,
VDD = 12 V,
VSS = – 5 V
VSS = – 12 V
VSS = – 5 V
VSS = – 12 V
MIN
4
10
TYP†
4.5
10.8
– 4.4
– 10.7
–4
– 10
1
–1
– 19 5
19.5
19.5
19 5
250
250
– 250
– 250
MAX
UNIT
V
V
µA
µA
mA
mA
µA
µA
No load All inputs at 2 V or 0 8 V
load,
0.8
No load All inputs at 2 V or 0 8 V
load,
0.8
ro
Output resistance
VDD = VSS = VCC = 0,
VO = – 2 V to 2 V,
See Note 3
300
400
Ω
† All typical values are at TA = 25°C.
‡ Not more than one output should be shorted at one time.
NOTES: 2. The algebraic convention, where the more positive (less negative) limit is designated as maximum, is used in this data sheet for logic
levels only.
3. Test conditions are those specified by EIA/TIA-232-E.
switching characteristics, V
DD
= 12 V, V
SS
= –12 V, V
CC
= 5 V
±10%,
T
A
= 25°C
PARAMETER
tPLH
tPHL
tTLH
tTHL
tTLH
tTHL
Propagation delay time, low- to high-level
output§
Propagation delay time, high- to low-level
output§
Transition time, low- to high-level output¶
Transition time, high- to low-level output¶
Transition time, low- to high-level output#
Transition time, high- to low-level output#
RL = 3 to 7 kΩ,
CL = 15 pF,
See Figure 3
0.53
0.53
RL = 3 to 7 kΩ,
RL = 3 to 7 kΩ,
CL = 2500 pF,
CL = 2500 pF,
See Figure 3
See Figure 3
TEST CONDITIONS
MIN
TYP
1.2
2.5
2
2
1
1
MAX
3
3.5
3.2
3.2
2
2
UNIT
µs
µs
µs
µs
µs
µs
SR
Output slew rate
RL = 3 to 7 kΩ, CL = 15 pF,
See Figure 3
4
10
30
V/µs
§ tPHL and tPLH include the additional time due to on-chip slew rate control and are measured at the 50% points.
¶ Measured between 10% and 90% points of output waveform.
# Measured between 3 V and – 3 V points of output waveform (EIA/TIA-232-E conditions) with all unused inputs tied either high or low.
4
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