SSM6K404TU
TOSHIBA Field-Effect Transistor Silicon N-Channel MOS Type
SSM6K404TU
○
High-Speed Switching Applications
○
Power Management Switch Applications
•
•
1.5-V drive
Low ON-resistance:
R
DS(ON)
= 147 mΩ (max) (@V
GS
= 1.5 V)
R
DS(ON)
= 100 mΩ (max) (@V
GS
= 1.8 V)
R
DS(ON)
= 70 mΩ (max) (@V
GS
= 2.5 V)
R
DS(ON)
= 55 mΩ (max) (@V
GS
= 4.0 V)
2.1±0.1
1.7±0.1
Unit: mm
0.65 0.65
Absolute Maximum Ratings (Ta = 25˚C)
Characteristic
Drain–source voltage
Gate–source voltage
Drain current
Power dissipation
Channel temperature
Storage temperature
DC
Pulse
Symbol
V
DSS
V
GSS
I
D
I
DP
P
D
(Note 1)
T
ch
T
stg
Rating
20
±
10
3.0
6.0
500
150
−55
to 150
Unit
V
V
A
mW
°C
°C
1.3±0.1
1
2
3
6
5
4
0.7±0.05
1, 2, 5, 6 : Drain
3
4
: Gate
: Source
Using continuously under heavy loads (e.g. the application of
high temperature/current/voltage and the significant change in
temperature, etc.) may cause this product to decrease in the
reliability significantly even if the operating conditions (i.e.
operating temperature/current/voltage, etc.) are within the
absolute maximum ratings.
Please design the appropriate reliability upon reviewing the
Toshiba Semiconductor Reliability Handbook (“Handling
Precautions”/“Derating Concept and Methods”) and individual
reliability data (i.e. reliability test report and estimated failure
rate, etc).
Note 1: Mounted on an FR4 board
2
(25.4 mm
×
25.4 mm
×
1.6 mm, Cu Pad: 645 mm )
Note:
UF6
JEDEC
JEITA
TOSHIBA
―
―
2-2T1D
Weight: 7.0 mg (typ.)
Electrical Characteristics
(Ta
=
25°C)
Characteristic
Drain–source breakdown voltage
Drain cutoff current
Gate leakage current
Gate threshold voltage
Forward transfer admittance
Symbol
V
(BR) DSS
V
(BR) DSX
I
DSS
I
GSS
V
th
⏐Y
fs
⏐
Test Condition
I
D
=
1 mA, V
GS
=
0 V
I
D
=
1 mA, V
GS
=
-10 V
V
DS
=20
V, V
GS
=
0 V
V
GS
= ±10
V, V
DS
=
0 V
V
DS
=
3 V, I
D
=
1 mA
V
DS
=
3 V, I
D
=
2.0 A
I
D
=
2.0 A, V
GS
=
4.0 V
Drain–source ON-resistance
R
DS (ON)
I
D
=
2.0 A, V
GS
=
2.5 V
I
D
=
1.0 A, V
GS
=
1.8 V
I
D
=
0.5 A, V
GS
=
1.5 V
Input capacitance
Output capacitance
Reverse transfer capacitance
Total Gate Charge
Gate−Source Charge
Gate−Drain Charge
Switching time
Turn-on time
Turn-off time
C
iss
C
oss
C
rss
Q
g
Q
gs
Q
gd
t
on
t
off
V
DSF
V
DS
= 10 V, I
D
= 3.0 A
V
GS
= 4 V
V
DS
= 10 V, I
D
= 2.0 A
V
GS
= 0 to 2.5 V, RG = 4.7
Ω
I
D
=
- 3.0 A, V
GS
=
0 V
(Note2)
V
DS
=
10 V, V
GS
=
0 V, f
=
1 MHz
(Note2)
(Note2)
(Note2)
(Note2)
(Note2)
Min
20
12
⎯
⎯
0.35
5.5
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Typ.
⎯
⎯
⎯
⎯
⎯
11
43
53
67
82
400
68
60
5.9
4.1
1.8
14
15
-0.85
Max
⎯
⎯
1
±1
1.0
⎯
55
70
100
147
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
-1.2
ns
V
nC
pF
mΩ
Unit
V
V
μA
μA
V
S
Drain–source forward voltage
Note 2: Pulse test
1
2010-01-26
+0.06
0.16-0.05
+0.1
0.3-0.05
2.0±0.1
SSM6K404TU
Switching Time Test Circuit
(a) Test Circuit
2.5 V
0
10
μs
V
DD
=
10 V
R
G
=
4.7
Ω
Duty
≤
1%
V
IN
: t
r
, t
f
<
5 ns
Common Source
Ta
=
25°C
OUT
IN
R
G
0V
V
DD
10%
(b) V
IN
2.5 V
90%
(c) V
OUT
V
DD
90%
10%
t
r
t
on
t
f
t
off
V
DS (ON)
Marking
6
5
4
Equivalent Circuit
(top view)
6
5
4
KKB
1
2
3
1
2
3
Notice on Usage
V
th
can be expressed as the voltage between gate and source when the low operating current value is I
D
= 1 mA for
this product. For normal switching operation, V
GS (on)
requires a higher voltage than V
th
and V
GS (off)
requires a lower
voltage than V
th.
(The relationship can be established as follows: V
GS (off)
< V
th
< V
GS (on).
)
Take this into consideration when using the device.
Handling Precaution
When handling individual devices that are not yet mounted on a circuit board, make sure that the environment is
protected against electrostatic discharge. Operators should wear antistatic clothing, and containers and other objects that
come into direct contact with devices should be made of antistatic materials.
2
2010-01-26
SSM6K404TU
I
D
– V
DS
6
4.0 V
2.5 V
1.8 V
10
Common Source
VDS
=
3 V
Pulse test
I
D
– V
GS
(A)
(A)
I
D
Drain current
5
1.5 V
4
1
I
D
Drain current
0.1
Ta
=
100 °C
0.01
25 °C
0.001
−
25 °C
3
2
V
GS
= 1.2 V
1
Common Source
Ta
=
25 °C
Pulse test
0.2
0.4
0.6
0.8
1.0
0
0.0001
0
1.0
2.0
Drain–source voltage
V
DS
(V)
Gate–source voltage
V
GS
(V)
R
DS (ON)
– V
GS
200
ID
=2.0A
Common Source
Pulse test
200
Common Source
Ta
=
25°C
Pulse test
R
DS (ON)
– I
D
Drain–source ON-resistance
R
DS (ON)
(mΩ)
100
Drain–source ON-resistance
R
DS (ON)
(mΩ)
100
1.5V
1.8 V
2.5 V
V
GS
= 4.0 V
25 °C
Ta
=
100 °C
−
25 °C
0
0
2
4
0
0
2
6
8
4
6
Gate–source voltage
V
GS
(V)
Drain current
I
D
(A)
R
DS (ON)
– Ta
200
Common Source
Pulse test
1.0
V
th
– Ta
Common Source
VDS
=
3 V
ID
=
1 mA
V
th
(V)
1.0 A / 1.8 V
Drain–source ON-resistance
R
DS (ON)
(mΩ)
0.8
Gate threshold voltage
0.5A / 1.5 V
0.6
100
2.0A / 2.5 V
0.4
ID
=
2.0 A / VGS
=
4.0 V
0.2
0
−50
0
50
100
150
0
−50
0
50
100
150
Ambient temperature
Ta
(°C)
Ambient temperature
Ta
(°C)
3
2010-01-26
SSM6K404TU
r
th
1000
Single Pulse
–
t
w
1000
P
D
– T
a
Power dissipation P
D
(mW)
Mounted on FR4 board
(25.4mm × 25.4mm × 1.6mm ,
2
Cu Pad : 645 mm )
t
=
10 s
800
rth (°C/W)
Transient thermal impedance
100
Mounted on FR4 board
2
(25.4mm × 25.4mm × 1.6mm , Cu Pad : 645 mm )
600
DC
400
10
200
1
0.001
0.01
0.1
1
10
100
1000
0
-40
-20
0
20
40
60
80
100 120 140 160
Pulse width
t
w
(s)
Ambient temperature
Ta
(°C)
5
2010-01-26
FPGA/CPLD
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