19-2576; Rev 0; 10/02
One-to-Five LVPECL/LVCMOS Output Clock and
Data Driver
General Description
The MAX9324 low-skew, low-jitter, clock and data driver
distributes a differential LVPECL input to four differential
LVPECL outputs and one single-ended LVCMOS output.
All outputs default to logic low when the differential inputs
equal GND or are left open. The MAX9324 operates from
3.0V to 3.6V, making it ideal for 3.3V systems, and con-
sumes only 25mA (max) of supply current.
The MAX9324 features low 150ps (max) part-to-part
skew, low 15ps output-to-output skew, and low 1.7ps
RMS jitter, making the device ideal for clock and data
distribution across a backplane or board. CLK_EN and
SEOUT_Z control the status of the various outputs.
Asserting CLK_EN low configures the differential (Q_,
Q_)
outputs to a differential low condition and SEOUT to
a single-ended logic-low state. CLK_EN operation is
synchronous with the CLK_ inputs. A logic high on
SEOUT_Z places SEOUT in a high-impedance state.
SEOUT_Z is asynchronous with the CLK (CLK) inputs.
The MAX9324 is available in space-saving 20-pin
TSSOP and ultra-small 20-pin 4mm
✕
4mm thin QFN
packages and operates over the extended (-40°C to
+85°C) temperature range.
o
1.7ps
RMS
Added Random Jitter
o
150ps (max) Part-to-Part Skew
o
450ps Propagation Delay
o
Synchronous Output Enable/Disable
o
Single-Ended Monitor Output
o
Outputs Assert Low when CLK,
CLK
are Open or
at GND
o
3.0V to 3.6V Supply Voltage Range
o
-40°C to +85°C Operating Temperature Range
Features
o
15ps Differential Output-to-Output Skew
MAX9324
Ordering Information
PART
MAX9324EUP
MAX9324ETP*
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
20 TSSOP
20 Thin QFN-EP**
Applications
Precision Clock Distribution
Low-Jitter Data Repeater
Data and Clock Driver and Buffer
Central-Office Backplane Clock Distribution
DSLAM Backplane
Base Station
ATE
CLK_EN
*Future
product—Contact factory for availability.
**EP
= Exposed paddle.
Functional Diagram and Typical Operating Circuit appear at
end of data sheet.
Pin Configurations
GND
N.C.
Q0
17
TOP VIEW
20
19
18
16
GND 1
20 Q0
19 Q0
18 V
CC
17 Q1
CLK_EN 2
N.C. 3
SEOUT 4
GND 5
12 Q2
11 Q2
N.C. 6
SEOUT_Z 7
CLK 8
Q0
SEOUT 1
GND 2
N.C. 3
SEOUT_Z 4
CLK 5
15 V
CC
14 Q1
MAX9324
**EXPOSED PADDLE
13 Q1
MAX9324
16 Q1
15 Q2
14 Q2
13 V
CC
12 Q3
11 Q3
6
CLK
7
V
CC
8
Q3
9
Q3
10
V
CC
CLK 9
V
CC
10
THIN QFN-EP** (4mm x 4mm)
**CONNECT EXPOSED PADDLE TO GND.
TSSOP
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
One-to-Five LVPECL/LVCMOS Output Clock and
Data Driver
MAX9324
ABSOLUTE MAXIMUM RATINGS
V
CC
to GND ...........................................................-0.3V to +4.0V
Q_,
Q_,
CLK,
CLK,
SEOUT_Z, CLK_EN,
SEOUT to GND.......................................-0.3V to (V
CC
+ 0.3V)
CLK to
CLK
............................................................................±3V
SEOUT Short to GND .................................................Continuous
Continuous Output Current (Q_,
Q_)
..................................50mA
Surge Output Current (Q_,
Q_)
.........................................100mA
Continuous Power Dissipation (T
A
= +70°C)
20-Pin TSSOP (derate 11mW/°C)..............................879.1mW
20-Pin 4mm
✕
4mm Thin QFN (derate 16.9mW/°C)..1349.1mW
Junction-to-Ambient Thermal Resistance in Still Air
20-Pin TSSOP ............................................................+91°C/W
20-Pin 4mm
✕
4mm Thin QFN.................................+59.3°C/W
Junction-to-Case Thermal Resistance
20-Pin TSSOP ............................................................+20°C/W
20-Pin 4mm
✕
4mm Thin QFN......................................+2°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Soldering Temperature (10s) ...........................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 3.0V to 3.6V, differential outputs terminated with 50Ω ±1% to (V
CC
- 2V), SEOUT_Z = GND, CLK_EN = V
CC
, T
A
= -40°C to
+85°C, unless otherwise noted. Typical values are at V
CC
= 3.3V, T
A
= +25°C.) (Notes 1, 2, and 3)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
DIFFERENTIAL INPUT (CLK,
CLK)
Differential Input High Voltage
Differential Input Low Voltage
Differential Input Voltage
Input Current
DIFFERENTIAL OUTPUTS (Q_,
Q_)
Single-Ended Output High
Single-Ended Output Low
Differential Output Voltage
Output High Voltage
Output Low Voltage
Output High-Impedance Current
Output Short-Circuit Current
SUPPLY
Supply Current
I
CC
(Note 4)
25
mA
SINGLE-ENDED OUTPUT (SEOUT)
V
OH
V
OL
I
OZ
I
OS
I
OH
= -4mA
I
OL
= 4mA
SEOUT_Z = V
CC
, SEOUT = V
CC
or GND
V
CLK
= V
CC
, SEOUT = GND
-10
2.4
0.4
+10
75
V
V
µA
mA
V
IHD
V
ILD
V
IHD
- V
ILD
I
CLK
V
OH
V
OL
V
OH
- V
OL
V
IHD
, V
ILD
Figure 1
Figure 1
Figure 1
Figure 1
Figure 1
1.5
0
0.15
-5
V
CC
- 1.4
V
CC
- 2.0
0.6
V
CC
V
CC
- 0.15
1.5
+150
V
CC
- 1.0
V
CC
- 1.7
0.85
V
V
V
µA
V
V
V
SYMBOL
V
IH
V
IL
I
IH
I
IL
CLK_EN = V
CC
SEOUT_Z = V
CC
CLK_EN = GND
SEOUT_Z = GND
-150
-5
+5
CONDITIONS
MIN
2
0
-5
TYP
MAX
V
CC
0.8
+5
150
UNITS
V
V
µA
µA
SINGLE-ENDED INPUTS (CLK_EN, SEOUT_Z)
2
_______________________________________________________________________________________
One-to-Five LVPECL/LVCMOS Output Clock and
Data Driver
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 3.0V to 3.6V, differential outputs terminated with 50Ω ±1% to (V
CC
- 2V), f
CLK
≤
266MHz, input duty cycle = 50%, input transi-
tion time = 125ps (20% to 80%), V
IHD
= 1.5V to V
CC
, V
ILD
= GND to (V
CC
- 0.15V), V
IHD
- V
ILD
= 0.15V to 1.5V, CLK_EN = V
CC
,
SEOUT_Z = GND, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at V
CC
= 3.3V, V
IHD
= (V
CC
- 1V), V
ILD
= (V
CC
-
1.5V), T
A
= +25°C.) (Note 5)
PARAMETER
Switching Frequency
Propagation Delay
Output-to-Output Skew
Part-to-Part Skew
Output Rise Time
Output Fall Time
Output Duty Cycle
Added Random Jitter
Added Deterministic Jitter
Added Jitter
Single-Ended Output Rise Time
Single-Ended Output Fall Time
Single-Ended Output Duty Cycle
SYMBOL
f
MAX
t
PHL
, t
PLH
t
SKOO
t
SKPP
t
R
t
F
ODC
t
RJ
t
DJ
t
AJ
t
R
t
F
ODC
f
CLK
= 650MHz (Note 9)
2e - 1 PRBS pattern, f = 650Mbps (Note 9)
V
CC
= 3.3V with 25mV superimposed
sinusoidal noise at 100kHz (Note 9)
C
L
= 15pF, 20% to 80%, Figure 1
C
L
= 15pF, 80% to 20%, Figure 1
(Note 10)
40
23
MAX9324
CONDITIONS
V
OH
- V
OL
≥
0.6V, SEOUT_Z = V
CC
SEOUT_Z = GND, SEOUT
CLK,
CLK
to Q_,
Q_,
Figure 1 (Note 6)
(Note 7)
(Note 8)
20% to 80%, Figure 1
80% to 20%, Figure 1
MIN
650
125
100
TYP
800
200
450
MAX
UNITS
MHz
600
30
150
ps
ps
ps
ps
ps
%
ps
(RMS)
ps
(P-P)
ps
(P-P)
ns
ns
%
100
100
48
217
207
50
1.7
83
8.5
1.6
1.6
52
300
300
52
3
100
12
2
2
60
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Measurements are made with the device in thermal equilibrium.
Current into a pin is defined as positive. Current out of a pin is defined as negative.
DC parameters are production tested at T
A
= +25°C and guaranteed by design over the full operating temperature range.
All pins open except V
CC
and GND.
Guaranteed by design and characterization. Limits are set at ±6 sigma.
Measured from the differential input signal crosspoint to the differential output signal crosspoint.
Measured between the differential outputs of the same part at the differential signal crosspoint for a same-edge transition.
Measured between the differential outputs of different parts at the differential signal crosspoint under identical conditions
for a same-edge transition.
Note 9:
Jitter added to the input signal.
Note 10:
Measured at 50% of V
CC
.
_______________________________________________________________________________________
3
One-to-Five LVPECL/LVCMOS Output Clock and
Data Driver
MAX9324
Typical Operating Characteristics
(V
CC
= 3.3V, outputs terminated to (V
CC
- 2V) through 50Ω, SEOUT_Z = V
CC
, CLK_EN = V
CC
, T
A
= +25°C.)
SUPPLY CURRENT vs. TEMPERATURE
MAX9324 toc01
DIFFERENTIAL OUTPUT AMPLITUDE
(V
OH
- V
OL
) vs. FREQUENCY
700
OUTPUT AMPLITUDE (mV)
600
500
400
300
200
100
0
0
200 400 600 800 1000 1200 1400 1600
FREQUENCY (MHz)
MAX9324 toc02
14.0
13.5
SUPPLY CURRENT (mA)
13.0
12.5
12.0
11.5
11.0
10.5
10.0
-40
-15
10
35
60
800
85
TEMPERATURE (°C)
DIFFERENTIAL OUTPUT RISE/FALL TIME
vs. TEMPERATURE
MAX9324 toc03
DIFFERENTIAL PROPAGATION DELAY
vs. TEMPERATURE
DIFFERENTIAL PROPAGATION DELAY (ps)
500
490
480
470
460
450
440
430
420
410
-40
-15
10
35
60
85
t
PHL
t
PLH
MAX9324 toc04
250
DIFFERENTIAL OUTPUT RISE/FALL TIME (ps)
240
230
220
210
200
190
180
170
160
150
-40
-15
10
35
60
t
F
t
R
510
85
TEMPERATURE (°C)
TEMPERATURE (°C)
4
_______________________________________________________________________________________
One-to-Five LVPECL/LVCMOS Output Clock and
Data Driver
Pin Description
PIN
TSSOP
1, 5
QFN
2, 18
NAME
GND
FUNCTION
Ground. Provide a low-impedance connection to the ground plane.
Synchronous Output Enable. Connect CLK_EN to V
CC
or leave floating to enable the
differential outputs. Connect CLK_EN to GND to disable the differential outputs. When
disabled, Q_ asserts low,
Q_
asserts high, and SEOUT asserts low. A 51kΩ pullup resistor to
V
CC
allows CLK_EN to be left floating.
No Connect. Not internally connected.
LVCMOS/LVTTL Clock Output. SEOUT reproduces CLK when SEOUT_Z = GND. SEOUT
goes high impedance when SEOUT_Z = V
CC
. The maximum output frequency of SEOUT is
125MHz.
Single-Ended Clock Output Enable/Disable. Connect SEOUT_Z to GND to enable the single-
ended clock output. Connect SEOUT_Z to V
CC
to disable the single-ended clock output. A
51kΩ pulldown resistor to GND allows SEOUT_Z to be left floating.
Noninverting Differential LVPECL Input. An internal 51kΩ pulldown resistor to GND forces the
outputs (Q_,
Q_)
to differential low and logic low (SEOUT) when CLK and
CLK
are left open or
at GND and the outputs are enabled.
Inverting Differential LVPECL Input. An internal 51kΩ pulldown resistor to GND forces the
outputs (Q_,
Q_)
to differential low and logic low (SEOUT) when CLK and
CLK
are left open or
at GND and the outputs are enabled.
Positive Supply Voltage. Bypass V
CC
to GND with three 0.01µF and one 0.1µF ceramic
capacitors. Place the 0.01µF capacitors as close to each V
CC
input as possible (one per V
CC
input). Connect all V
CC
inputs together, and bypass to GND with a 0.1µF ceramic capacitor.
Inverting Differential LVPECL Output. Terminate
Q3
to (V
CC
- 2V) with a 50Ω ±1% resistor.
Noninverting Differential LVPECL Output. Terminate Q3 to (V
CC
- 2V) with a 50Ω ±1% resistor.
Inverting Differential LVPECL Output. Terminate
Q2
to (V
CC
- 2V) with a 50Ω ±1% resistor.
Noninverting Differential LVPECL Output. Terminate Q2 to (V
CC
- 2V) with a 50Ω ±1% resistor.
Inverting Differential LVPECL Output. Terminate
Q1
to (V
CC
- 2V) with a 50Ω ±1% resistor.
Noninverting Differential LVPECL Output. Terminate Q1 to (V
CC
- 2V) with a 50Ω ±1% resistor.
Inverting Differential LVPECL Output. Terminate
Q0
to (V
CC
- 2V) with a 50Ω ±1% resistor.
Noninverting Differential LVPECL Output. Terminate Q0 to (V
CC
- 2V) with a 50Ω ±1% resistor.
MAX9324
2
19
CLK_EN
3, 6
4
3, 20
1
N.C.
SEOUT
7
4
SEOUT_Z
8
5
CLK
9
6
CLK
10, 13, 18
11
12
14
15
16
17
19
20
7, 10, 15
8
9
11
12
13
14
16
17
V
CC
Q3
Q3
Q2
Q2
Q1
Q1
Q0
Q0
_______________________________________________________________________________________
5
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